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Downlink bit-level processing method based on fpga hardware acceleration

A downlink and hardware acceleration technology, applied in electrical components, program control, instruments, etc., can solve the problems of data disorder and loss design difficulty, increase of mobile communication system delay, and reduce algorithm design difficulty, etc., to achieve real-time high-speed The effect of processing, real-time improvement and delay reduction

Active Publication Date: 2022-07-01
BEIJING UNIV OF POSTS & TELECOMM +1
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Problems solved by technology

[0003] At present, in PDSCH bit-level FPGA design, the serial data transmission method will reduce the difficulty of module algorithm design, but will increase the delay of the entire mobile communication system
In addition, the bit-level FPGA code design of PDSCH needs to consider complex timing logic, and the problem of data disorder and loss brings difficulties to the design

Method used

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  • Downlink bit-level processing method based on fpga hardware acceleration
  • Downlink bit-level processing method based on fpga hardware acceleration

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Embodiment Construction

[0011] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0012] The existing general-purpose processor platform implements the operation processing of the entire link on the CPU, which takes a lot of time when faced with complex calculations. The invention realizes the downlink bit-level data processing by FPGA, thereby reducing the signal processing time delay, and improving the processing capability of the large-capacity data of the virtualized gateway station and the real-time performance of communication transmission.

[0013] like figure 1 As shown, the downlink PDSCH bit-level processing method based on FPGA hardware acceleration of the present invention is realized based on the combination of a general-purpose processing platform CPU and a hardware accelerator FPGA; wherein, the general-purpose processing platform CPU mainly completes the selection of the communication transmission system, th...

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Abstract

The present invention is a downlink bit-level processing method based on FPGA hardware acceleration, which can be applied to the large-capacity real-time signal and protocol processing of the LTE-based satellite mobile communication virtual gateway station. The present invention realizes the functions of the MAC layer and above in the CPU; on the hardware accelerator FPGA, the data to be transmitted adopts an 8-bit parallel transmission architecture and passes through a data processing module, a transmission block CRC24A adding module, a code block segmentation parameter calculation module, and a code block CRC24B adding module. After processing and transmission, bit collection, selection and pruning are carried out after parallel-serial conversion, turbo coding module, code block interleaving module, and finally the code blocks are cascaded and output to complete the bit-level data processing of the entire PDSCH channel. The invention reduces the signal processing time delay and improves the processing capability of the large-capacity data of the virtualized gateway station and the real-time performance of communication transmission.

Description

technical field [0001] The invention belongs to the technical field of mobile communication, and in particular relates to a technology for realizing LTE (Long Term Evolution) physical layer bit-level data processing using FPGA (Field Programmable Logic Gate Array), which can be applied to LTE-based satellite mobile communication virtual gateway High-capacity real-time signal and protocol processing for stations. Background technique [0002] With the evolution of satellite mobile communication systems, large-capacity data transmission puts forward higher demands on communication resources, computing resources and storage resources of satellite gateways. The MAC (Media Access Control) layer in the satellite mobile communication system needs to complete tasks such as resource scheduling, multiplexing, demultiplexing, HARQ (Hybrid Automatic Repeat Request) and random access, which is a heavy processing burden for the MAC layer. Therefore, under the premise of ensuring the corr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00G05B19/042
CPCH04L1/0071H04L1/0061H04L1/0068H04L1/0057G05B19/0423
Inventor 王程徐闻璐张志丽王卫东
Owner BEIJING UNIV OF POSTS & TELECOMM
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