Self-calibrating frequency quadrupler and method thereof

Abstract

The invention relates to a self-calibrating frequency quadrupler and method thereof. The quadrupler comprises a main frequency quadrupler configured to receive a first clock and output a second clockof a quadruple frequency in accordance with a first control signal and a second control signal, wherein a timing difference between a first rising edge and a second rising edge of the second clock iscontrolled by the second control signal, and a timing difference between the first rising edge and a third rising edge of the second clock is controlled by the first control signal; an auxiliary frequency quadrupler configured to receive the first clock and output a third clock of the quadruple frequency with a timing offset controlled a third control signal; and a calibration circuit configured to generate and output the first control signal, the second control signal, and the third control signal in accordance with a timing difference between the second clock and the third clock.

Description

technical field [0001] The invention relates to frequency quadrupling technology, and in particular to a frequency quadrupling device with a self-correction mechanism and a method thereof. Background technique [0002] In this disclosure, a clock signal is a signal that periodically switches back and forth between a high state level and a low state level; a positive edge occurs when the clock signal transitions from a low state level to a high state level; When the clock signal transitions from a high-state level to a low-state level; a cycle of the clock signal starts with a positive edge and ends with the next positive edge (which is also the beginning of the next cycle), and is included in the positive edge and The negative edge between the times of the next positive edge; the pulse width in one cycle of a clock signal is the time difference between the beginning positive edge and the negative edge in that cycle; the period of one cycle of a clock signal is the beginning ...

AI Technical Summary

Problems solved by technology

The problem with the PLL 150 is that although the third clock signal S C The average frequency of , can be precisely established as a quadruple frequency, but the third clock signal S C The instantaneous time may be slightly different from the ideal time

In practice, low-noise VCOs require a large amount of power, or require high cost, or both.

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