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FPGA implementation method and system of a FARROW type filter

An implementation method and filter coefficient technology, applied in the field of FPGA implementation system, can solve the problems of high price ratio of bit width and high price ratio of ROM resources, and achieve the effect of small error, reduced possibility of overflow, and resource saving.

Active Publication Date: 2019-06-18
深圳市极致汇仪科技有限公司
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  • Application Information

AI Technical Summary

Problems solved by technology

For a filter with a relatively large numerator and denominator, the ROM resources in the FPGA consumed by this method are more expensive
Moreover, the bit width ratio of the entire quantization is large, and the overflow of the intermediate cumulative calculation needs special consideration

Method used

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  • FPGA implementation method and system of a FARROW type filter
  • FPGA implementation method and system of a FARROW type filter
  • FPGA implementation method and system of a FARROW type filter

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Embodiment Construction

[0035] The preferred embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0036] Such as figure 1 As shown, this example provides an FPGA implementation method of a FARROW type filter, including the following steps:

[0037] Step S1, set the filter coefficient coeff of the FARROW type filter according to 2 k Quantify;

[0038] Step S2, according to the calculation error interval u k The interpolation base point m generated when k Perform multiplication and accumulation operations with the quantized filter coefficient coeffL;

[0039] Step S3, the error interval u between the result after the multiplication and accumulation operation and the calculation k Do multiplication and addition.

[0040] In step S1 described in this example, by formula coeffL=floor(coeff·2 k / T s ) Quantize the filter coefficient coeff of the FARROW type filter to obtain the quantized filter coefficient coeffL, where flo...

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Abstract

The invention provides an FPGA implementation method and system of a FARROW type filter. The FPGA implementation method of the FARROW type filter comprises the following steps that S1, quantizing filter coefficients of the FARROW type filter; S2, carrying out multiplication and accumulation operation according to an interpolation base point generated during error interval calculation and the quantized filter coefficient; and S3, performing multiplication and addition operation on the result after the multiplication and accumulation operation and the calculated error interval. Error intervals and interpolation base points are generated in real time, and a large number of ROM resources which are not used in the FPGA implementation process of the FARROW type filter are reduced; On the basis,only one time of quantization of the filter coefficient is needed, equivalently, under the condition of the same quantization bit width, the error of amplitude-frequency response is smaller, and the possibility of overflowing is effectively reduced.

Description

technical field [0001] The invention relates to an FPGA realization method, in particular to an FPGA realization method of a FARROW type filter, and an FPGA realization system adopting the FPGA realization method of the FARROW type filter. Background technique [0002] For the method of sampling rate conversion, a multi-phase structure is generally used to realize it, but in some application scenarios, this method will be very inefficient. For example, it is necessary to do a sampling rate conversion with a fractional multiple of 1023 / 511. If a polyphase structure is used to realize it, 1023 sub-filters are required to realize it. The order of such a filter will be very large, and the direct result is that a large-capacity Rom is required to store the coefficients of the filter for fractional multiple and integer multiple filters, and at the same time consumes a lot of logic resources. [0003] The current general practice is to use a polynomial interpolation filter to achi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
CPCY02E40/40
Inventor 吴帅肖闽华
Owner 深圳市极致汇仪科技有限公司
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