Asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC

Abstract

The invention discloses an asynchronous clock generation circuit suitable for a 2-bit-per-cycle SAR ADC, and the circuit comprises a comparator conversion completion marking signal generation unit, agate control signal generation unit, an intermediate comparator judgement completion marking signal generation unit and a comparator asynchronous clock generation unit, wherein an output signal of thecomparator conversion completion marking signal generation unit and a conversion clock Conv are taken as input signals of the gate control signal generation unit; an output signal Q2 / QB2 of the intermediate comparator of the 2-bit-per-cycle SAR ADC is the input signal of the intermediate comparator judgement completion marking signal generation unit; the output signals of the gate control signalgeneration unit and the intermediate comparator judgement completion marking signal generation unit are taken as input signals of the comparator asynchronous clock generation unit; and the output signal of the comparator asynchronous clock generation unit is taken as an asynchronous clock of a first comparator, a second comparator and a third comparator. By such circuit provided by the invention,under a condition of realizing high-speed data conversion, use of an external clock of which a rate is several times higher than a sampling rate is avoided, and a problem of liability of a synchronousmetastable state is avoided at the same time.

Description

technical field [0001] The invention belongs to the technical field of analog-digital hybrid integrated circuits, and in particular relates to an asynchronous clock generation circuit suitable for 2-bit-per-cycle SAR ADC. Background technique [0002] The asynchronous successive approximation analog-to-digital converter (SAR ADC) is widely used because of its low power consumption, high digitization, and no need for multiplier clocks. However, the traditional asynchronous SAR ADC is essentially a serial structure, that is, the working principle of 1-bit-per-cycle known to the public, which greatly limits its application in high-speed applications. In recent years, the research on speed-up of SAR ADC is in full swing. [0003] Among them, in 2015, Hyeok-Ki Hong of the Korean Academy of Science and Technology proposed a 2-bit-per-cycle synchronous 7-bit SAR ADC in the Journal of Solid-State Circuits (JOURNAL OF SOLID-STATE CIRCUITS), which requires 5 times the sampling freque...

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Problems solved by technology

[0003] Among them, in 2015, Hyeok-Ki Hong of the Korean Academy of Science and Technology proposed a 2-bit-per-cycle synchronous 7-bit SAR ADC in the Journal of Solid-State Circuits (JOURNAL OF SOLID-STATE CIRCUITS), which requires 5 times the sampling frequency The external clock, and in order to correct the problems caused by the metastable state, digital correction technology is used, which may require the use of digital back-end technology, which increases the system complexity and design difficulty

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