Method for adjusting bus timing, storage medium and terminal

Abstract

The invention discloses a method for adjusting bus timing, a storage medium and a terminal. The method comprises the steps of obtaining a plurality of delay threshold values corresponding to a preset storage card; on the condition that a preset operation fails, detecting whether one delay threshold value capable of completing the preset operation exists in the multiple delay threshold values or not under the current first bus frequency, wherein the preset operation includes a read operation and / or a write operation of the preset storage card; on the condition that the delay threshold value capable of completing the preset operation exists, setting the delay threshold value as a delay threshold value under the first bus frequency, and according to the delay threshold value, adjusting a deviation between a clock signal and a two-way instruction or a response signal or a data signal so as to achieve data transmission. According to the method for adjusting bus timing, the function of traversing all delay threshold values under the bus frequency can be achieved, the read-write performance of the preset storage card is kept, and the problems in the prior art are solved.

Description

technical field [0001] The invention relates to the communication field, in particular to a method for adjusting bus timing, a storage medium and a terminal. Background technique [0002] At present, storage devices are widely used, for example, SD card (Secure Digital Memory Card, Secure Digital Memory Card), eMMC (Embedded Multi Media Card, Embedded Multi Media Card) and SDIO (Secure Digital Input and Output Card, Secure Digital Input and Output Card) . In order to increase the data transmission rate, the bus frequency of these storage devices is getting higher and higher. For example, the bus frequency in eMMC HS400 mode reaches 400MHz, and the bus frequency in SD / SDIO SDR104 mode reaches 208MHz. Timing issues arise when the bus frequency reaches hundreds of MHz. [0003] The SD / eMMC / SDIO bus is composed of CLOCK (clock signal), CMD (bidirectional command and response signal) and DATA (data signal) signal lines. CLOCK is used as a clock signal to ensure that the deviat...

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Problems solved by technology

[0007] The main purpose of the present invention is to propose a method for adjusting bus timing, a storage medium and a terminal, aiming to solve the following problems in the prior art: when the corresponding delay threshold in the rate mode supported by the memory card frequently causes read and write failures, Need to reduce the bus frequency corresponding to the memory card, thus affecting the read and write speed of the memory card

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