Mode classification method for dimensional check results of flat panel display layout

Abstract

The invention discloses a mode classification method for dimensional check results of a flat panel display layout, belongs to the field of semiconductor integrated circuit design automation, and mainly relates to how to classify the dimensional check results and improve manual screening efficiency. The dimensional check of the flat panel display layout uses an integrated circuit layout for reference, but a handling situation is more complex, and not all violation results need to be subjected to layout modification. At present, violation result screening depends on artificial judgment, and the violation results needed to be subjected to layout modification are screened out from all hundreds of thousands of results, so that the working efficiency is very low. According to the method, the results violating the dimensional check and surrounding environments are defined as mode features, and result categories are classified according to the mode features, so that hundreds of thousands of the results can be classified into dozens of to hundreds of categories. During manual screening, each category only needs to be judged once, so that the workload is reduced to the scale of dozens of to hundreds of the categories from hundreds of thousands of the results, the layout check efficiency is remarkably improved, the iterative modification cycle of the layout is shortened, and the design process is accelerated.

Description

technical field [0001] The invention discloses a method for classifying the results pattern of layout spacing inspection on a flat panel display, which belongs to the field of semiconductor integrated circuit design automation, and mainly relates to how to classify the spacing inspection results and improve the efficiency of manual screening. Background technique [0002] Dimensional Check (Dimensional Check) is an important part of electronic design automation. It originates from the integrated circuit layout (Integrated Circuit, IC) design process. It usually checks items such as wire width (Width) and wire spacing (Space), and the output The result is a design that violates spacing rules. Before the layout is delivered for tape-out, all designs that violate the rules must be iteratively modified to ensure successful tape-out. [0003] The spacing inspection of the flat panel display (FPD) layout is based on the layout of the integrated circuit, but the situation is more ...

AI Technical Summary

Problems solved by technology

[0006] Aiming at the field of semiconductor integrated circuit design automation, the invention proposes a pattern classification of the flat panel display layout spacing inspection results, which has low work efficiency and delays the entire layout design process due to the low work efficiency of manually screening the inspection results after performing the spacing check on the flat panel display layout. method

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