FPGA storage resource testing system, method and device

Abstract

The invention relates to an FPGA storage resource testing system, method and device. The system comprises a clock management module, a data excitation module, a clock domain crossing data transmission module, a data comparison module, and a result display module. The clock management module is used for providing a first clock signal for the data excitation module and the result display module, and providing a second clock signal for the data comparison module and a to-be-stored resource in the FPGA chip. The time frequency of the second clock signal is higher than the clock frequency of the first clock signal. The clock domain crossing data transmission module is used for achieving the data transmission of the time domain of the first clock signal and the time domain of the second clock signal. The system can improve the test time sequence convergence characteristics.

Description

technical field [0001] The present invention relates to the technical field of programmable logic array (FPGA), in particular to an FPGA storage resource testing system, method and device. Background technique [0002] Due to its programmable, flexible and high throughput characteristics, FPGA is widely used in the fields of digital signal acquisition, compression, transmission and processing. In order to verify whether the FPGA meets the expected technical indicators, it is necessary to test the FPGA device. According to the different test purposes, it can be divided into standard test and high touch test. The standard test is to verify the compliance of the FPGA device with the technical indicators, and the high touch test is to verify the margin of the FPGA device exceeding the expected technical indicators, which reflects the Actual performance of FPGA devices. [0003] When the traditional method is used to test the on-chip storage resources of the FPGA device, the in...

AI Technical Summary

Problems solved by technology

However, for high-speed FPGA devices, when the speed of the on-chip memory resources of the FPGA to be tested is getting higher and higher, other resources except the memory resource module to be tested limit the improvement of the test speed, so timing convergence is difficult to guarantee, the limit The speed test is difficult to achieve, and it is difficult to guarantee the test quality

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