Bit stream readback-based FPGA (field programmable gate array) testing platform

Abstract

The invention relates to a bit stream readback-based FPGA (field programmable gate array) testing platform. The testing platform has a bit stream analysis capability based on the boundary scanning function and bit stream readback function of an FPGA (field programmable gate array) manufactured by the Xilinx. A whole testing system, except a JTAG (joint test action group) interface, is completed in a computer. The testing system is not limited by the number of external IOB pins of the FPGA. Testing excitation can be applied directly through boundary scanning. A node for recovering test response is built into a D flip-flop and an LUT, so that the occupation of the resources of the FPGA and labor costs can be greatly decreased; and bit stream readback and bit stream analysis can achieve the detection and positioning of a fault more accurately.

Description

technical field [0001] The invention relates to bit stream readback technology, and the low-cost FPGA test platform realized can be effectively used in FPGA mass production test. Background technique [0002] The traditional FPGA test method is to design the corresponding test circuit based on the logic resources and architecture of the FPGA itself, and manufacture the test circuit PCB board, and complete the test through multiple test processes manually. This method is specifically to complete the configuration of the FPGA internal circuit through HDL code and generate a bit stream file, then download the bit stream file to the FPGA by EDA software, and then generate the corresponding signal through the peripheral circuit on the PCB board or an external signal generator. Test incentives, and finally use an oscilloscope or LED digital tube to judge whether the test response is correct. The entire process is complex and needs to be implemented manually, and the FPGA test nee...

AI Technical Summary

Problems solved by technology

Although this method avoids the disadvantage of needing to embed BIST circuits in the BIST-based method to occupy the internal resources of the FPGA, the speed is slow because the input or output of boundary scan data is serially completed.

And due to the limited number of FPGA chip IOs, the number of input test stimuli and recovered test responses is also limited, thereby increasing the design difficulty of the FPGA test circuit and the number of tests

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