FPGA heterogeneous acceleration system, data transmission method and FPGA

Abstract

The invention discloses a FPGA heterogeneous acceleration system comprising a FPGA and a PCIe drive end; the FPGA comprises DMAs of a first preset number and a request queue corresponding to each DMA; the PCIe drive end comprises service threads of a second preset number; the service thread is used for checking whether the corresponding request queue is empty or not, and if yes, a new request is added to the corresponding request queue, and the corresponding DMA is started for data transmission; the DMA is used for processing requests in sequence in the corresponding request queue, and an interrupt is sent to the PCIe drive end after each request is processed so as to prompt the data transmission is finished; the DMAs can commonly carry out data transmission, thus maximumly improving PCIe bus utilization rate, improving data transmission speed, and ensuring a reliable speed for a heterogeneous acceleration algorithm; the invention also discloses a FPGA heterogeneous acceleration data transmission method and the FPGA having said benefits.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a data transmission method for FPGA heterogeneous acceleration, FPGA and FPGA heterogeneous acceleration system. Background technique [0002] Heterogeneous acceleration requires extremely high data transmission speed, otherwise the purpose of computing acceleration will not be achieved. In the heterogeneous acceleration design, the transmission mode of single queue, single DMA and interrupt is generally adopted. Such as figure 1 As shown, in the DMA transmission method, due to the fast data copy and slow memory lock, the logic on the FPGA side is in a waiting state after the data is copied, so the utilization rate of the bus is not high, which affects the speed of data transmission in heterogeneous acceleration. Therefore, how to improve the utilization rate of the bus, and then improve the data transmission speed in the heterogeneous acceleration, is a technical probl...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, in the DMA transmission method, due to the fast data copy and slow memory lock, the logic on the FPGA side is in a waiting state after the data is copied, so the utilization rate of the bus is not high, which affects the speed of data transmission in heterogeneous acceleration.

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