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A planar grid igbt and its manufacturing method

A planar gate and gate electrode technology, applied in the field of planar gate insulated gate bipolar transistors and insulated gate bipolar transistors, can solve the problems of increasing device switching loss, reducing device switching speed, device oscillation, etc.

Inactive Publication Date: 2018-09-04
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The gate structure on the upper part of the wide JFET region brings large device capacitance, especially the gate-collector capacitance, which reduces the switching speed of the device, increases the switching loss of the device, and improves the ability of the gate drive circuit of the device. Require
In addition, the gate capacitance on the upper part of the JFET region of the device will form a negative differential capacitance effect when the device is turned on with a small current, which will cause the device to oscillate during the turn-on process and thus cause electromagnetic radiation problems

Method used

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  • A planar grid igbt and its manufacturing method
  • A planar grid igbt and its manufacturing method
  • A planar grid igbt and its manufacturing method

Examples

Experimental program
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Effect test

Embodiment 1

[0044] A planar gate IGBT, its semi-cellular structure and the section along the AB line are as follows figure 2 with image 3 As shown, it includes: the back collector metal 10, the P-type collector region 9 located on the back collector metal 10 and connected to it, the N-type field stop layer 8 located on the P-type collector region 9 and connected to it, The N-drift region 7 located on the N-type field stop layer 8 and connected to it; the p-type base region 4 located on both sides of the upper part of the N-drift region 7 and connected to it, and the upper part of the p-type base region 4 and connected to each other Independent N+ emitter region 3 and P+ emitter region 2; emitter metal 1 located on the upper surface of N+ emitter region 3 and P+ emitter region 2; compound gate structure and floating p-type region located on the semiconductor surface between emitter metal 1 11. It is characterized in that: the composite gate structure includes a dielectric layer 5 and a ...

Embodiment 2

[0046] A planar gate IGBT, its semi-cellular structure and the cross-section along the AB and CD lines are as follows Figure 4 , Figure 5 with Image 6 As shown, on the basis of Embodiment 1, the gate electrode 6 also has a left-right symmetrical interdigitated finger at the center of the half-cell in the direction perpendicular to the length of the MOS channel. The length of the interdigitated fingers in the direction parallel to the length of the MOS channel is 3-5 microns, and the length in the direction perpendicular to the length of the MOS channel is 5-10 microns. The presence of the interdigitated fingers of the gate electrode 6 further enhances the lateral carrier diffusion from the gate to the emitter connection electrode, improving forward conduction characteristics and carrier concentration distribution.

Embodiment 3

[0048] A planar gate IGBT, its semi-cellular structure and the cross-section along the AB and CD lines are as follows Figure 7 , Figure 8 with Figure 9 As shown, on the basis of Example 2, there is also a layer of N-type N-type on the surface of the JFET region between the floating P-type regions 11, both sides of the floating P-type regions 11 and the p-type base region 4. Layer 12, the doping concentration of the N-type layer 12 is greater than the concentration of the N-drift region 7, and its junction depth is 0.1-0.3 microns smaller than the junction depth of the floating P-type region 11. The introduction of the N-type buried layer 15 further improves the forward conduction characteristics and carrier concentration distribution of the device. When the device breaks down, the N-type buried layer 15 is fully depleted.

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Abstract

A planar gate IGBT and a manufacturing method thereof belong to the technical field of power semiconductor devices. Based on the traditional planar gate IGBT device structure, the present invention introduces a floating p-type region in a part of the surface of the JFET region of the device, and the floating p-type region and the gate electrode form an interval distribution perpendicular to the length of the MOS channel. When the device is forward-conducting, the JFET region diffuses lateral carriers from the gate to the floating p-type region in the direction perpendicular to the length of the MOS channel. The structure of the present invention reduces the forward conduction characteristics of the device without affecting the The gate capacitance of the device is reduced, especially the gate-collector capacitance, which improves the switching speed of the device and reduces the switching loss of the device without deteriorating the blocking characteristics of the device.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to an insulated gate bipolar transistor (IGBT), in particular to a planar gate insulated gate bipolar transistor. Background technique [0002] Insulated Gate Bipolar Transistor (IGBT) is a new type of power electronic device combining MOS field effect and bipolar transistor. It not only has the advantages of easy driving and simple control of MOSFET, but also has the advantages of low conduction voltage of power transistor, large on-state current and small loss. It has become one of the core electronic components in modern power electronic circuits and is widely used in Various fields of the national economy such as communications, energy, transportation, industry, medicine, household appliances and aerospace. The application of IGBT plays an extremely important role in improving the performance of power electronic systems. [0003] Since the invention of IGBT, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/417H01L29/423H01L29/66H01L29/739
CPCH01L29/41708H01L29/42356H01L29/66333H01L29/7395
Inventor 张金平张玉蒙田丰境刘竞秀李泽宏任敏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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