Batched random mechanism for chip random verification

A random verification and mechanism technology, which is applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of unreachable scenes and decreased scene diversity, and achieve the effect of accelerating verification convergence

Inactive Publication Date: 2016-06-01
SHANDONG HAILIANG INFORMATION TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the number of incentives for a random verification is too small, it is likely that many scenarios that should be covered cannot be covered; if there are too many incentives, because the same set of random constraints is used, the diversity of the generated scenarios increases exponentially over time decline
In addition, the "appropriate number of incentives" will continue to change with the current verification level and specific random constraints, and the exact number cannot be obtained by analysis and past experience

Method used

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  • Batched random mechanism for chip random verification
  • Batched random mechanism for chip random verification

Examples

Experimental program
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Effect test

Embodiment 1

[0025] A batch-based random mechanism for chip random verification. Considering the possible impact of the number of random incentives on verification efficiency under specific random constraints in chip random verification, the efficiency of random verification in ultra-large-scale chip verification will vary with the As the simulation time increases, it decreases exponentially, and a single random verification is divided into several batches of verification serial execution, each batch of verification contains a certain number of incentives, and the efficiency evaluation of the current random verification is provided between different batches of verification And the control mechanism, so that the random constraint and the corresponding random incentive scale can be modified according to the change of verification efficiency. That is to say, the random verification will run under the specific random constraints before the verification efficiency decreases to a certain level, o...

Embodiment 2

[0028] Such as figure 2 As shown, on the basis of Embodiment 1, the implementation process of the random mechanism described in this embodiment is as follows:

[0029] 1) Quantify the generation constraints of random incentives; ensure that the modification of random constraints can be automatically completed through programs or scripts;

[0030] 2) Random incentives are generated in batches; generating random incentives in batches is different from generating all random incentives at the same time or with the same set of random constraints. Only a part (batch) of incentives is generated each time according to the current random constraints; each batch of The number of incentives can be fixed or not; the advantage of a fixed number of incentives is that it is easy to control, and if some appropriate algorithms are used to control the number of incentives between different batches, random verification of batches can be realized more flexibly. Which one is used? The method nee...

Embodiment 3

[0035] On the basis of Embodiment 2, the evaluation standard of the verification efficiency described in this embodiment: evaluate through defined coverage (code coverage or function point coverage).

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Abstract

The invention discloses a batched random mechanism for chip random verification. Single random verification is divided into multiple batches of verification to be executed in series, each batch of verification comprises multiple numbers of excitation, efficiency evaluation and a control mechanism on current random verification are provided among different batches of the verification, and random constraint and a corresponding random excitation scale can be modified according to changes of the verification efficiency. According to the batched random mechanism for the chip random verification, the problem that in the random verification, proper excitation numbers need to be determined on specific random constraint is solved, a large amount of resource waste caused by too many excitation numbers cannot occur, and insufficient verification caused by too small excitation numbers cannot occur either. Great significance in accelerating a verification closure and controlling a chip development cycle is achieved.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a batch random mechanism for chip random verification. Background technique [0002] With the continuous development of process technology and application fields, the complexity of chips continues to increase, and correspondingly, the complexity of verification work also continues to increase. The importance of random verification is also increasing, and improving the efficiency of random verification has also become a key step to improve verification efficiency. [0003] Random constraints are used in the application of random verification. Different random constraints represent different characteristics of random verification. They complement each other with the verification effect evaluation criteria (generally coverage) used in verification, ensuring that random verification will not fail due to excessive divergence. The efficiency is too low. [0004] However, in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/30
Inventor 李拓周恒钊符云越
Owner SHANDONG HAILIANG INFORMATION TECH RES INST
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