URL blocking method based on FPGA and TCAM

Abstract

The invention discloses a URL blocking method based on an FPGA and a TCAM, and relates to an information blocking method. The method employs a Hash algorithm to compress an URL keyword with combining with TCAM matching, and can meet the requirements for the URL blocking at a large-flow line speed.

Description

Technical field [0001] The invention relates to an information blocking method, in particular to a URL blocking method based on FPGA and TCAM. Background technique [0002] URL (UniformResourceLocator, Uniform Resource Locator) blocking is to restrict access to certain specific URLs. The traditional URL blocking is to establish a URL library, directly compare and match specific URL fields, and perform subsequent processing such as discarding the successfully matched messages. It is mainly applied to software development platforms such as CPU / GPU / network processor. In the prior art, URL matching and blocking on a single CPU / GPU / network processor can only achieve a processing performance of tens to hundreds of kPPS, while the backbone network 10G port needs to achieve a processing performance of 14.4Mpps. The prior art Unable to meet the URL matching and blocking requirements under high traffic line speed. Summary of the invention [0003] In view of the above-mentioned shortcomin...

AI Technical Summary

Problems solved by technology

The prior art can only achieve the processing performance of tens of k to hundreds of kPPS for URL matching and blocking on a single CPU / GPU / network processor, while the 10G port of the backbone network needs to achieve the processing performance of 14.4Mpps. Unable to meet the URL matching and blocking requirements under large traffic line speed

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