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A Method of Optimizing the Power Consumption of Three-valued FPRM Circuit Using Exhaustive Method

An exhaustive method and circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of multi-valued RM circuit power consumption optimization technology that has not been studied.

Active Publication Date: 2017-09-29
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, experts and scholars at home and abroad mainly focus on the polarity conversion technology of multi-valued RM logic circuits, and have not studied the power consumption optimization technology of multi-valued RM circuits.

Method used

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  • A Method of Optimizing the Power Consumption of Three-valued FPRM Circuit Using Exhaustive Method

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Embodiment 1

[0038] Embodiment one: a kind of ternary FPRM circuit power consumption optimization method utilizing exhaustive method, comprises the steps:

[0039] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0040] ①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0041]

[0042] Among them, n is the function f p (x n-1 ,x n-2 ,...,x 0 ), the number of variables for x n-1 ,x n-2 ,...,x 0 represents the function f p (x n-1 ,x n-2 ,...,x 0 ) of n input variables, p represents the function f p (x n-1 ,x n-2 ,...,x 0 ) polarity, the polarity p is expressed as p in n-bit ternary form n-1 p n-2 …p 0 ,p j ∈{0,1,2}, j=0,1,2,...,n-1, ⊕ means multi-input modulo 3 addition operation, ∑ is the accumulation symbol, the symbol "*" means the multiplication sign, i=0,1 ,2,…,3 n -1, i is expressed as i in n-digit ternary form n-1 i n-2 …i 0 , i j ∈{0,1,2},a i is the FPRM coeffic...

Embodiment 2

[0062] Embodiment two: a kind of ternary FPRM circuit power consumption optimization method utilizing exhaustive method, comprises the following steps:

[0063] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0064] ①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0065]

[0066] Among them, n is the function f p (x n-1 ,x n-2 ,...,x 0 ), the number of variables for x n-1 ,x n-2 ,...,x 0 represents the function f p (x n-1 ,x n-2 ,...,x 0 ) of n input variables, p represents the function f p (x n-1 ,x n-2 ,...,x 0 ) polarity, the polarity p is expressed as p in n-bit ternary form n-1 p n-2 …p 0 ,p j ∈{0,1,2}, j=0,1,2,...,n-1, ⊕ means multi-input modulo 3 addition operation, ∑ is the accumulation symbol, the symbol "*" means the multiplication sign, i=0,1 ,2,…,3 n -1, i is expressed as i in n-digit ternary form n-1 i n-2 …i 0 , i j ∈{0,1,2},a i is the FP...

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Abstract

The invention discloses a method for optimizing the power consumption of a ternary FPRM circuit using an exhaustive method. Firstly, the ternary FPRM circuit is represented by a ternary FPRM logic function under p polarity, and then the ternary FPRM logic function contained in the ternary FPRM logic function is decomposed Multi-input operation, obtain multiple two-input modulo 3-add gates and multiple two-input modulo 3-multiply gates under p polarity, and use the power consumption caused by two-input modulo 3-add gates and two-input modulo 3-multiply gates as p polarity Based on the power consumption of the ternary FPRM circuit below, the power consumption estimation model of the ternary FPRM circuit is constructed. Finally, the exhaustive method is used to search for the best polarity of power consumption of the ternary FPRM circuit, and the minimum power consumption of the ternary FPRM circuit is obtained by searching. The best polarity of power consumption and power consumption; the advantage is that the power consumption optimization of the ternary FPRM circuit can be realized; 13 MCNC Benchmark circuits are randomly used for simulation verification, and the best polarity searched by the present invention is compared with 0 polarity, modulo 3 The average number of added gates is saved by 54.94%, the average number of modular 3-multiplied gates is saved by 46.89%, and the average power consumption is saved by 72.72%. The power consumption optimization effect is remarkable.

Description

technical field [0001] The invention relates to a method for optimizing the power consumption of a ternary FPRM circuit, in particular to a method for optimizing the power consumption of a ternary FPRM circuit using an exhaustive method. Background technique [0002] With the continuous development of the scale and integration of integrated circuits, digital circuits will inevitably encounter problems such as power consumption, area and speed. Traditional digital circuits mostly use binary logic, but the low information content of binary signals has become the main factor restricting the development of integrated circuits. The multi-valued logic circuit increases the ability to carry information in a single line, which can effectively improve the utilization rate of space or time, reduce the connection of digital systems, and save circuit area and cost. The three-valued logic whose base is 3 has the smallest base in the algebraic system of multi-valued logic, which is easy ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 汪鹏君厉康平张会红
Owner NINGBO UNIV
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