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A Method for Optimum Polarity Search of Power Consumption in Ternary FPRM Circuit

A search method and power consumption technology, applied in the direction of error correction/detection using linear codes, data representation error detection/correction, error correction/detection using block codes, etc. conducting research, etc.

Active Publication Date: 2017-09-29
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, experts and scholars at home and abroad mainly focus on the polarity conversion technology of multi-valued RM logic circuits, and have not studied the power consumption optimization technology of multi-valued RM circuits.

Method used

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  • A Method for Optimum Polarity Search of Power Consumption in Ternary FPRM Circuit
  • A Method for Optimum Polarity Search of Power Consumption in Ternary FPRM Circuit
  • A Method for Optimum Polarity Search of Power Consumption in Ternary FPRM Circuit

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Embodiment 1

[0059] Embodiment one: a kind of ternary FPRM circuit power consumption optimal polarity searching method comprises the following steps:

[0060] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0061]①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0062]

[0063] Among them, n is the function f p (x n-1 ,x n-2 ,...,x 0 ), the number of input variables, x n-1 ,x n-2 ,...,x 0 represents the function f p (x n-1 ,x n-2 ,...,x 0 ) of n input variables, p represents the function f p (x n-1 ,x n-2 ,...,x 0 ), the polarity p is expressed as p in ternary form n-1 p n-2 …p 0 ,p j ∈{0,1,2}, j=0,1,2,...,n-1, Indicates the modulo 3 addition operation, ∑ is the accumulation symbol, the symbol "*" is the multiplication operation symbol, and the subscript i=0,1,2,...,3 n -1, i is represented as i in ternary form n-1 i n-2 …i 0 , a i is the FPRM coefficient; a i ∈{0,...

Embodiment 2

[0094] Embodiment two: a kind of ternary FPRM circuit power consumption optimum polarity search method, comprises the following steps:

[0095] ①Establish the power consumption estimation model of the ternary FPRM circuit:

[0096] ①-1 The three-valued FPRM circuit is expressed as the following form using the three-valued FPRM logic function:

[0097]

[0098] Among them, n is the function f p (x n-1 ,x n-2 ,...,x 0 ), the number of input variables, x n-1 ,x n-2 ,...,x 0 represents the function f p (x n-1 ,x n-2 ,...,x 0 ) of n input variables, p represents the function f p (x n-1 ,x n-2 ,...,x 0 ), the polarity p is expressed as p in ternary form n-1 p n-2 …p 0 ,p j ∈{0,1,2}, j=0,1,2,...,n-1, Indicates the modulo 3 addition operation, ∑ is the accumulation symbol, the symbol "*" is the multiplication operation symbol, and the subscript i=0,1,2,...,3 n -1, i is represented as i in ternary form n-1 i n-2 …i 0 , a i is the FPRM coefficient; a i ∈{0,1...

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Abstract

The invention discloses a method for searching the optimal polarity of the power consumption of a ternary FPRM circuit. Firstly, the ternary FPRM circuit is represented by a ternary FPRM logic function under p polarity, and then decomposed into multiple components contained in the ternary FPRM logic function. Input operation, obtain multiple two-input modulo 3 addition gates and multiple two-input modulo 3 multiplication gates under p polarity, and use the power consumption caused by two-input modulo 3 addition gates and two-input modulo 3 multiplication gates as p polarity The power consumption of the ternary FPRM circuit is constructed to obtain the power consumption estimation model of the ternary FPRM circuit. Finally, the simulated annealing genetic algorithm is used to search the optimal polarity of the power consumption of the ternary FPRM circuit, and the optimal polarity search and Minimum power consumption; the advantage is to realize the optimal polarity search of the power consumption of the ternary FPRM circuit, thereby realizing the optimization of the power consumption of the ternary FPRM circuit; randomly adopting 13 MCNC Benchmark circuits for simulation verification, the best polarity of the power consumption searched by the present invention Compared with 0 polarity, the average number of modulo 3 multiplication gates is saved by 57.64%, the number of modulo 3 multiplication gates is saved by an average of 46.25%, and the average power consumption is saved by 73.98%.

Description

technical field [0001] The invention relates to a method for optimizing the power consumption of a ternary FPRM circuit, in particular to a method for searching the best polarity of the power consumption of a ternary FPRM circuit. Background technique [0002] With the continuous development of the scale and integration of integrated circuits, digital circuits will inevitably encounter problems such as power consumption, area and speed. Traditional digital circuits mostly use binary logic, but the low information content of binary signals has become the main factor restricting the development of integrated circuits. The multi-valued logic circuit increases the ability to carry information in a single line, which can effectively improve the utilization rate of space or time, reduce the connection of digital systems, and save circuit area and cost. The three-valued logic whose base is 3 has the smallest base in the algebraic system of multi-valued logic, which is easy to impl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/13
Inventor 厉康平汪鹏君张会红
Owner NINGBO UNIV
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