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IIC bus experimental facility debugged by serial port

An experimental device, serial port debugging technology, applied in the fields of instruments, electrical digital data processing, computing, etc., can solve the problems of inability to guarantee safety and accuracy, complex debugging, etc., to achieve simple and easy-to-understand operation instructions, saving hardware resources, simple effect

Inactive Publication Date: 2015-03-11
TIANJIN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This new method described by this inventor allows for faster testing without requiring complex steps like connecting external devices or reconnecting cables between different components on an electronic system's motherboard. It eliminates any mistakes that may occur during previous methods such as writing code downward from memory into RAM before transmitting it over another wireline connection. Instead, these older techniques were limited because they required manual input and could lead to incorrect results when trying to connect other parts together due to their complexity.

Problems solved by technology

This patented technical problem addressed in this patents relates to improving the efficiency and reliability of connecting different types of digital components together without requiring extra connections like cables that may be expensive at lower speeds than necessary due to their large size.

Method used

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  • IIC bus experimental facility debugged by serial port
  • IIC bus experimental facility debugged by serial port
  • IIC bus experimental facility debugged by serial port

Examples

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Embodiment Construction

[0015] A structure of an IIC bus experimental device debugged through a serial port mainly includes four parts: an upper computer UART interface controller, a protocol conversion unit, an IIC bus interface controller and a clock management unit, such as figure 2 shown.

[0016] The upper computer UART interface controller is used to communicate with the upper computer, responsible for receiving the serial data from the upper computer through the UART protocol and converting it into parallel data, and at the same time sending the parallel data to the upper computer serially through the UART protocol; The protocol conversion unit is responsible for the communication and coordination between the UART interface controller and the IIC bus interface controller and the transfer control of the system state machine; the IIC bus interface controller is responsible for receiving instructions, peripheral addresses, register addresses and data, if the instruction is write, then Write the ...

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Abstract

The invention relates to a communication bus experimental facility; for solving the defect that the current IIC bus is complex in debugging and cannot ensure safety and accuracy when in data transmission, the invention provides an IIC bus experimental facility debugged by a serial port, which can visually check through a command editing window of an upper computer or modifying data of a register of external equipment, and visually display the obtained return value at a PC end. According to the communication bus experimental facility, the original advantages of IIC is ensured, and furthermore, operators can more conveniently and clearly use an IIC protocol to debug a test chip. Therefore, the technical scheme adopted by the invention includes that the IIC bus experimental facility debugged by the serial port includes an upper computer UART interface controller, a protocol converting unit, an IIC bus interface controller and a clock management unit. The IIC bus experimental facility debugged by the serial port is mainly applied to bus tests.

Description

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Claims

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Application Information

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Owner TIANJIN UNIV
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