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Novel test development method for improving simultaneous test number

A new technology of simultaneous measurement, which is applied in the field of new test development to improve the same measurement, to achieve a high effect of simultaneous measurement

Active Publication Date: 2014-11-05
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to achieve the above-mentioned technical purpose, according to the present invention, a novel test development method for improving the number of tests is provided, which includes: a first step for receiving test requirements; a second step for evaluating test requirements so as to target the chip The pins group and classify the test requirements; the third step is to evaluate whether the grouped and classified pins can share the test channel; wherein, in the third step, it is judged that the grouped and classified pins cannot share the test channel In this case, return to the second step; in the third step, it is judged that the grouped and classified pins can share the test channel, and the fourth step is executed; the fourth step is used to confirm the same measurement number

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  • Novel test development method for improving simultaneous test number
  • Novel test development method for improving simultaneous test number

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Embodiment Construction

[0017] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0018] In order to clearly explain the novel test development method of the present invention, first briefly introduce the flow of the test development method in the prior art. figure 2 A flow chart of a test development method according to the prior art is schematically shown. Such as figure 2 As shown, in the prior art, the test development method generally includes: receiving test requirements; evaluating the number of resources required by a single chip; evaluating test machine resources; confirming the number of tests; probe card design and production; test program development; test program commissioning; and final wafer testing.

[0019] Responsively, image 3 A flow chart of a novel test development method for increasing the number o...

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Abstract

A novel test development method for improving a simultaneous test number comprises the following steps that firstly, test requirements are received; secondly, the test requirements are assessed and then pins of a chip can be conveniently grouped and classified according to the test requirements; thirdly, whether the grouped and classified pins can share a test passage is assessed, the second step is repeated when the grouped and classified pins can not share the test passage, and the fourth step is executed when the grouped and classified pins can share the test passage; fourthly, the simultaneous test number is confirmed; fifthly, a probe card is designed and manufactured; sixthly, a test program is developed; seventhly, the test program is debugged; eighthly, a wafer is tested. Under the condition that the resources of a test machine are not changed, by means of the test developed method, the simultaneous test number can be largely improved on the premise of guaranteeing the test quality, the total test time is shortened, and test efficiency is improved.

Description

technical field [0001] The invention relates to the field of chip functional testing in the field of microelectronics, and more specifically, the invention relates to a novel test development method for improving the number of simultaneous tests. Background technique [0002] The pins of the chip can basically be divided into input pins, output pins, power supply pins, ground pins and so on. In the process of using an automatic test machine such as T2000 to test chips, the pins of each chip need to occupy special test machine channel resources. These test machine channel resources will generate chip input waveforms (input vectors) and comparisons according to test requirements. Whether the output waveform of the chip is correct, etc., such as figure 1 shown. In the traditional co-test design, the pins of each chip occupy one channel resource of the testing machine, so the number of co-testing that can be realized can be estimated as follows: the number of testing co-testin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 李强蔡恩静王继华高金德
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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