Hybrid-structured memory array and method of making the same

Abstract

The invention relates to the field of semiconductor devices, and discloses a memory array with a mixed structure and a preparation method thereof. In the memory array of the mixed structure of the present invention, the difference between the structure of the ROM unit and the structure of the flash memory unit lies in the channel injection, the connection between the gate and the floating gate, and the presence or absence of electrodes, and only three layers of photomasks need to be modified, namely 2T pMOS flash memory cells can be converted into ROM cells, so the free combination of flash memory arrays and ROM arrays with different capacities can be realized under the premise of the same process and the same area, and the appearance of flash memory arrays and ROM arrays is almost the same , The position distribution can be adjusted at will, while significantly reducing the production cost, it greatly increases the scope of application of the product and the market adaptability, and effectively improves the safety level of the product.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a memory array with a mixed structure and a preparation method thereof. Background technique [0002] Embedded Flash Memory (Embedded Flash Memory) is usually integrated into a system-level chip in the form of an IP core (Intellectual Property Core, intellectual property core), such as a mobile phone SIM-card (SIM is an abbreviation for Subscriber Identity Module, referring to a customer identification module) chip , Smart bank card chips, etc. Because of this feature, it is called "embedded" to distinguish it from products formed by Stand-alone Flash Memory. [0003] However, the inventors of the present invention have found that existing embedded chips also have the following problems: [0004] 1. The existing embedded flash technology has high complexity (30-40 layers of photomasks) and long production cycle (40-60 days); [0005] 2. Taking bank financial IC card produc...

AI Technical Summary

Problems solved by technology

Such a layout allows the product cracker to take some specific measures (such as laser irradiation, temperature control, electrical interference, etc.) for the ROM array or flash memory array, and at the same time monitor the response changes of the entire chip system (such as power consumption, specific circuit timing, etc.) etc.), and then obtain the specific storage location of the key instructions of the microcontroller product operating system (usually stored in the ROM array) or user key information (usually stored in the flash memory array) and the corresponding system response, which may eventually lead to the product being cracked, the product data has been tampered with

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