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Hybrid dram memory and method for reducing power consumption when the dram memory is refreshed

A memory and main memory technology, applied in the fields of instruments, electrical digital data processing, energy-saving computing, etc., can solve the problems of no reduction in refresh power consumption, increase in cost, and high process requirements, and achieve lower refresh power consumption, lower power consumption, and higher The effect of refresh cycles

Active Publication Date: 2017-06-13
SHANGHAI XINCHU INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this structure has very high requirements on the process and increases the cost, and the DRAM still needs to be refreshed regularly, and the refresh power consumption has not been reduced.

Method used

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  • Hybrid dram memory and method for reducing power consumption when the dram memory is refreshed
  • Hybrid dram memory and method for reducing power consumption when the dram memory is refreshed

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Embodiment 1

[0055] Although the ability of the end memory cells to hold data is very poor, the hold time of more than 99% of the memory cells can reach more than 1s. Based on the above analysis, the present invention proposes a structure of a hybrid DRAM memory, Figure 7 It is a structural schematic diagram of the hybrid DRAM memory of the present invention; as Figure 7 As shown, the hybrid DRAM memory includes a DRAM main memory, a non-volatile memory and a logic detection module, and the DRAM main memory is connected with the logic detection module in bidirectional communication, and can detect the working status of the DRAM main memory, such as The access frequency and refresh frequency of the DRAM main memory. If the access frequency is greater than or equal to the refresh frequency, it indicates that the DRAM main memory is in a busy state, and the DRAM main memory operates in the original refresh mode, and the refresh cycle is the second refresh time. At this time, the logic detec...

Embodiment 2

[0060] This embodiment discloses a method for implementing a hybrid dynamic random access memory, Figure 9 For the flow chart that the hybrid DRAM memory function of the present invention realizes; As Figure 9 As shown, its methods include:

[0061] Step 1: The logic detection module detects the data storage time of each storage unit at intervals, and divides the storage units into tail storage units and main storage units according to the detected data storage time of the storage units.

[0062] Step 2: When the hybrid DRAM memory is in a normal working state, the logic detection module will detect the working state of the DRAM main memory: that is, whether the DRAM main memory is in a busy state, such as the DRAM main memory access frequency is greater than or equal to the refresh frequency of the hybrid DRAM. The power consumption of the hybrid DRAM is mainly from the access to the hybrid DRAM, and the refresh power consumption of the hybrid DRAM can be ignored. At this...

Embodiment 3

[0067] The hybrid DRAM memory structure in this embodiment is applied to non-volatile dynamic memory (NVDIMM) (such as image 3 ) products, the purpose is to reduce the refresh power consumption of the internal DRAM main memory. Compared with the original NVDIMM, the DRAM main memory is periodically refreshed at the original refresh frequency, and the refresh time is the second refresh time, which consumes a lot of refresh power. After power-off, the non-volatile memory is used to store the data in the DRAM main memory after power-off Data, the data in the non-volatile memory is transferred back to the DRAM main memory after power-on.

[0068] Figure 10 It is a schematic structural diagram of Embodiment 3 of the present invention; as Figure 10 shown. For example: the capacity of the DRAM main memory is 1GB, which is divided into 8 DRAM blocks, each DRAM block contains several storage units, and the capacity of the non-volatile memory is 1GB, which is used to replace the e...

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Abstract

The invention discloses a mixed DRAM storage and method of reducing refresh power consumption of the DRAM storage. A non-volatile storage is combined with a DRAM main storage, a specified storage cell of the non-volatile storage is used to replace a tail end storage cell of the DRAM main storage, so that a refresh cycle is greatly improved, refresh rate is reduced, and refresh power consumption of the DRAM main storage is reduced greatly.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices and integrated circuits, in particular to a hybrid DRAM memory and a method for reducing power consumption when the DRAM memory is refreshed. Background technique [0002] Over the past few decades, the cost of dynamic random access memory (DRAM) has continued to decrease with Moore's Law. However, as the feature size becomes smaller and smaller, the power consumption requirements of the chip are also higher and higher. Due to the leakage of the DRAM storage capacitor, it must be refreshed every once in a while, and the power consumption of the refresh is increased. For example, figure 1 As shown, the refresh power consumption of a DRAM with a smaller capacity will be lower, accounting for only a small part of the power consumption. However, as the DRAM capacity increases, the refresh power consumption will increase significantly. This is because the feature size shrinks and the powe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/28
CPCY02D10/00
Inventor 景蔚亮陈邦明
Owner SHANGHAI XINCHU INTEGRATED CIRCUIT
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