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High-speed cache block length adjusting method and device of high-speed cache memory

A high-speed cache and cache technology, applied in the computer field, can solve the problem that the length of the cacheline cannot be changed and adjusted, and achieve the effect of increasing the access rate and improving the system performance.

Active Publication Date: 2014-05-07
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a method and device for adjusting the cache block length of a cache memory to solve the problem that the cacheline length of a Cache cannot be changed and adjusted in the prior art

Method used

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  • High-speed cache block length adjusting method and device of high-speed cache memory
  • High-speed cache block length adjusting method and device of high-speed cache memory
  • High-speed cache block length adjusting method and device of high-speed cache memory

Examples

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Effect test

example 1

[0049] Example 1, Table 1 is the cache structure of the cacheline with a length of 32 bytes, and n=5 at this time;

[0050] Table 1

[0051]

[0052] image 3 It is a schematic diagram of a cache structure of a cacheline with a length of 32 bytes in an embodiment of the present invention, such as image 3 As shown, if the Cache size is 32k bytes, 32 sets are used. When the cacheline size is 32bytes, then each Set has 32 cachelines, that is, 32ways. If the starting address is 0x0, then way0 stores 0x00000000~0x000003ff; way1 stores 0x00000400~0x7ff; ..., Way31 stores 0x7c00~0x7fff. Among them, bit[31:13] indicates the first address of the way where the set is located, bit[12:5] indicates which cacheline it is, and bit[4:2] indicates the offset address of the word in the cacheline.

example 2

[0053] Example 2, table 2 is the structure of 64bytes cacheline length, n=6 at this time;

[0054] Table 2

[0055]

[0056] Figure 4 It is a schematic diagram of the cache structure of a cacheline with a length of 64 bytes in the embodiment of the present invention. In the cache, a set associative method is adopted to design the cache. If the Cache size is 32k bytes, then 32 sets are used. When the cacheline size is 64byte, then Each Set has 16 cachelines, that is, 32 ways. If the starting address is 0x0, then way0 stores 0x00000000~0x000003ff; way1 stores 0x00000400~0x7ff; ...; Way31 stores 0x7c00~0x7fff. Among them, bit[31:14] indicates the first address of the group (Set) t where the set is located, bit[15:6] indicates which cacheline it is, and bit[5:2] indicates the offset address of the word in the cacheline.

[0057] According to Example 1 and Example 2, the structural composition of the cache of other cacheline sizes can be obtained.

[0058] 2. The operation t...

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Abstract

The invention discloses a line length adjusting method and device for a high-speed cache of a high-speed cache memory. The method comprises the steps of cancelling and removing all of high-speed cached lines in the high-speed cache memory to enable the high-speed cache memory, adjusting the length of the high-speed cached lines to be smaller than a first preset length value smaller than the current length value and enabling the high-speed cache memory if continuous hit failure times of accessed data or instructions is larger than a first preset threshold value; cancelling and removing all of high-speed cached lines in the high-speed cache memory to enable the high-speed cache memory, adjusting the length of the high-speed cache blocks to be a second preset length value larger the current length value and enabling the high-speed cache memory if the times of continuously hit line in the high-speed cache memory is larger than a second preset threshold value and the data or the instructions in high-speed cache blocks after content filling are sequentially accessed when the data or the instructions are accessed.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method and device for adjusting the length of a cache block of a cache memory. Background technique [0002] At present, in the prior art, cache memory (Cache) technology is mainly considered from the local continuity of the program and the characteristic that the access rate of the cache is much faster than that of the next-level memory. figure 1 is a schematic diagram of the system storage structure in the prior art, such as figure 1 As shown, it includes: CPU, Cache, and bus interface, and the external storage device transmits data and address information through the bus interface. For a 32-bit wide system, when accessing a 4-byte instruction or data, the content (instruction or data) of a cache block (cacheline) length including this address is loaded into a cacheline at a time to ensure Instructions or data can be fetched directly from the cache for a period of time to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F12/04G06F12/0802G06F12/0864G06F12/0886G06F12/0888G06F12/0891G06F12/0893G06F12/121G06F12/126
CPCG06F12/0802G06F12/0864G06F12/0886G06F12/0888G06F12/0893G06F12/121G06F12/126G06F2212/601G06F11/141G06F12/0891G06F2201/885
Inventor 万志军
Owner SANECHIPS TECH CO LTD
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