Sampling device for timing analysis of logic analyzer

Abstract

The invention relates to a measuring technology of a forward channel, in particular to a signal test device for a forward channel of a logic analyzer. The sampling device for timing analysis of the logic analyzer comprises a displacement register, a high-speed difference interface, a parallel latch module, a high-speed clock and a low-speed clock. The displacement register is connected with the high-speed difference interface and the high-speed clock respectively. The high-speed difference interface is connected with the parallel latch module and the low-speed clock respectively. The high-speed clock is connected with the low-speed clock through a frequency divider. According to the design, a serial-parallel conversion scheme is adopted to achieve high-speed collection of signals, after one-time serial-parallel conversion is finished, the low-speed clock is used for sampling the parallel output of the latch register, and therefore the purpose of lowering the frequency of data processing work is achieved and the reliability of work of a system is improved.

Description

technical field [0001] The invention relates to a forward channel measurement technology, in particular to a signal testing device for the forward channel of a logic analyzer. Background technique [0002] Timing analysis sampling is to collect input data on the edge of the internal clock and work asynchronously with the system clock under test. Timing analysis sampling is usually implemented by directly writing the sampling data into the memory with registers and related control circuits. However, as the sampling rate of the design increases, the access speed of the memory greatly limits this simple method of directly storing the input data. For example, the highest sampling rate of 500M for timing analysis in this design requires that the corresponding memory read and write rate should be within 2ns / Byte, but the commonly used SRAM is still difficult to realize stably. Therefore, we need to choose a more effective data acquisition scheme, which not only meets the clock r...

AI Technical Summary

Problems solved by technology

However, as the sampling rate of the design increases, the access speed of the memory greatly limits this simple method of directly storing the input data

For example, the maximum sampling rate of

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