Parametric universal FIFO control method

Abstract

The invention relates to a parametric universal FIFO control method. The method includes the steps; 1, static input parameters are input to a universal FIFO control circuit; 2, internal variables required to implement the FIFO control circuit are obtained according to the static input parameters; 3, the required universal FIFO control circuit is achieved according to the internal variables generated in the step 2 and required by the FIFO control circuit. The preset parameter precompiling means has the advantages that the means can be reused in all designs requiring FIFO, and multiple designing is avoided; 'section Gray encoding' is utilized, namely a fixed incremental value is centrally added to read and write addresses, and accordingly the maximum and minimum binary Gray code converted from the incremental value is provided with different numerical sections under only one bit; Gray code transform is applied to the code, so that the depth can be any even.

Description

technical field [0001] The invention belongs to the technical field of computer hardware and relates to a circuit control method, in particular to a parameterized general FIFO control method. Background technique [0002] FIFO (First-In, First-out), that is, first-in-first-out memory, is divided into synchronous FIFO and asynchronous FIFO. It is a circuit device commonly used for data caching, and can be applied to high-speed data acquisition, multiprocessor interface and communication. Various fields such as high-speed buffering in According to different requirements and application environments, FIFOs may have different depths, different data bit widths, different read and write clock relationships, different empty and full indication methods, etc., usually need to be designed several times according to requirements, and asynchronous FIFOs generally Gray codes are used to compare the read and write addresses, which leads to the fact that if the FIFO depth is not a power o...

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Problems solved by technology

According to different requirements and application environments, FIFOs may have different depths, different data bit widths, different read and write clock relationships, different empty and full indication methods, etc., usually need to be designed several times according to requirements, and asynchronous FIFOs generally Gray codes are used to compare the read and write addresses, which leads to the fact that if the FIFO depth is not a power of 2, when the read and write addresses return from the maximum value (depth-1) to 0, the binary Gray code of the maximum value has multiple digits. When it is 1, when it changes back to all 0s, multiple bits will jump from 1 to 0, thus losing the advantage of only one bit jump in the adjacent code value of the Gray code, which will bring hidden dangers of metastable state, so the depth of asynchronous FIFO is usually limited to The power of 2 causes a waste of resources and is very inconvenient to use

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