Field programmable gata array (FPGA) based video de-noising method

A video and video frame technology, applied in the video field, can solve problems such as time domain blur, and achieve the effects of accurate threshold calculation, good compatibility and versatility

Active Publication Date: 2013-04-24
四川九洲投资控股集团有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But for moving images, moving objects will produce temporal blurring such as artifacts

Method used

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  • Field programmable gata array (FPGA) based video de-noising method
  • Field programmable gata array (FPGA) based video de-noising method
  • Field programmable gata array (FPGA) based video de-noising method

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Embodiment Construction

[0019] The specific embodiment of the present invention is:

[0020] Step 1: Use FPGA to store the input video sequence into the initial frame image in the external memory of the system.

[0021] Step 2: Build a 4×4 matrix generation module inside the FPGA, and calculate the MAD value of the corresponding matrix blocks of the two frames before and after;

[0022] The calculation method of MAD is as follows:

[0023] MAD = | Σ j = 0 3 Σ i = 0 3 ( CMB x , y ( i , j ) - PMB x , ...

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Abstract

The invention relates to a field programmable gata array (FPGA) based video de-noising method which comprises the steps: inputting the signal and outputting coder and decoder, choosing corresponding signal channel according to the inputted signal format, respectively obtaining each component signal in the inputted signal, inputting each component signal to a main algorithm, after the process of the algorithm, and combining each component signal as a demand signal. By means of the combination, different signal format conversion can be achieved, and time-domain infinite impulse response (IIR) filtering is utilized to a static area and a kinetic area. According to the FPGA based video de-noising method, in de-noising processing to each frame video image, a kinetic block and a static block are enabled to be subdivided in a spatial domain and to be processed respectively. From the time domain, dynamically calculating the threshold value according to mean square error of MAD in video frames, and dynamically analyzing movement of the video sequence, so that calculation of the threshold value is more accurate. In addition, due to the fact that FPGA is used for achieving de-noising algorithm, good compatibility and generality are possessed.

Description

technical field [0001] The invention relates to the video field, in particular to an FPGA-based video denoising method. Background technique [0002] At present, most of the dedicated chips are used for denoising at the front end of video processing. Due to the high price and single function of the dedicated chips, and the variety of video signal formats and noise types, they do not have good compatibility and versatility. Therefore, the programmability of the module is required, coupled with the rapid development of programmable technology, the use of FPGA to denoise video has been developed rapidly. [0003] At present, FPGA-based video denoising algorithms are mainly divided into two types: spatial filtering and temporal filtering. Spatial filtering often adopts the method of weighted average of adjacent pixels. Practice has proved that spatial filtering is not effective in removing noise and will sacrifice high-frequency details of the image, resulting in image distorti...

Claims

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Application Information

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IPC IPC(8): H04N5/21H04N7/26H04N19/122
Inventor 彭伟伦李汶隆刘念林周勇
Owner 四川九洲投资控股集团有限公司
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