Vertical parasitic type precision navigation processor (PNP) device and manufacturing method thereof in bipolar complementary metal-oxide-semiconductor transistor (BiCMOS) technology
A vertical parasitic and process technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the problems of large device area, shrinking device size, and large collector connection resistance, and achieve high current amplification factor, The effect of reducing the area and reducing the production cost
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[0034] Such as figure 1 Shown is a schematic structural view of the vertical parasitic PNP device in the BiCMOS process of the embodiment of the present invention. The vertical parasitic PNP device in the BiCMOS process of the embodiment of the present invention is formed on a P-type silicon substrate 1 and placed on the P-type silicon substrate 1. An N-type deep well 2 is formed on a silicon substrate 1, and the active region is isolated by a shallow trench field oxygen 3, which is shallow trench isolation (STI). The vertical parasitic PNP device includes:
[0035] A collector region 7 is composed of a P-type ion implantation region formed in the active region, and the depth of the collector region 7 is greater than or equal to the depth of the bottom of the shallow trench field oxygen 3 . The process conditions of the P-type ion implantation region of the collector region 7 and the CMOS P well are the same, and the implantation impurity of the P-type ion implantation of the ...
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