Power and area efficient interleaved ADC

Abstract

Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track- and-hold (T / H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with ''re-used'' or shared analog processing circuitry. Parallel track- and-hold (T / H) circuits (304, 306) receive an analog input signal (AIN or prior residue) and are clocked at half clock cycles (CLK / 2) by clocking circuit 303 to sample / hold on non- overlapping logic phases. The T / H circuits (304, 306) are respectively coupled to analog-to-digital converter (ADC 310) through multiplexer (308) and to digital-to-analog converter (DAC 312), adder (314) and amplifier (316) to perform analog processing to resolve sampled signals for digital output circuit (104) and to generate a residue signal (ROUT).

Description

technical field [0001] The present invention relates generally to analog-to-digital converters (ADCs), and more particularly to interleaved ADCs. Background technique [0002] High-performance ADCs typically do not obey the "Moore's Law" area and power curves of digital circuit implementations in ever-shrinking CMOS process technologies. The ADC's noise and resolution requirements dictate power constraints (lower noise requires higher power) and area constraints (exceeding parts matching requirements). Also, as ADC sampling rates increase, typical architectures cannot provide the required performance due to timing constraints. [0003] Referring to FIG. 1A of the drawings, reference numeral 100 generally designates a conventional ADC 100 . ADC 100 typically includes several stages 102 - 1 through 102 -N, ADC 106 (which is typically a flash ADC), and digital output circuitry 104 . Stages 102-1 through 102-N are typically coupled in series with one another in a sequence whe...

AI Technical Summary

Problems solved by technology

This arrangement allows relaxed timing because the sampled signal is held for the entire period of the clock signal CLK, but the addition of the T / H circuit 206 adds noise (ie, 3dB per T / H circuit 206)

To compensate for noise degradation, the power consumption of each T / H circuit 108 and 206 is doubled, resulting in four times the power consumption of a single T / H system

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