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Viterbi decoder and Viterbi decoding method

A Viterbi decoder and Viterbi decoding technology, applied in the field of Viterbi decoder and Viterbi decoding, can solve the problems of increasing path delay, reducing system operating clock, large register consumption, etc.

Inactive Publication Date: 2012-10-31
SONY CORP +1
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  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The half-fold slider processing mode can basically achieve a linear relationship between the increase in decoder speed and the amount of hardware overhead. However, in the case of a large constraint depth, due to the large number of encoding register state points, the register consumption in the Viterbi decoder Larger, and because the incoming data for forward and reverse sliders comes from the same bank of buffered shift registers, it causes routing congestion, spikes in path delays, and slows down system operating clocks

Method used

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  • Viterbi decoder and Viterbi decoding method

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Embodiment Construction

[0021] Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

[0022] In order to provide higher decoding rate and higher utilization of hardware resources, the present invention proposes a parallel Viterbi decoder and Viterbi decoding method based on forward sliding block mode.

[0023] image 3 A schematic block diagram of a Viterbi decoder according to an embodiment of the present invention is shown. As shown in the figure, the Viterbi decoder 300 includes a data manager 310 to be decoded, a plurality of ...

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Abstract

The invention discloses a Viterbi decoder and a Viterbi decoding method. The Viterbi decoder comprises a manager of data to be decoded, a plurality of Viterbi decoder units and a decoding data output manager, wherein the manager of the data to be decoded is used for distributing input data to be decoded to the plurality of Viterbi decoder units; each Viterbi decoder unit is used for independently carrying out Viterbi decoding based on a forward slide block mode on the distributed data to be decoded to obtain decoding data of the data to be decoded, wherein the data to be decoded, corresponding to each Viterbi decoder unit, comprises a synchronization block, a decoding block and a backtracking block which are successive; and the decoding data output manager is used for receiving corresponding decoding data from the plurality of Viterbi decoder units and combining and outputting the decoding data. According to the Viterbi decoder and the Viterbi decoding method, a higher decoding rate and a higher hardware resource utilization ration can be provided.

Description

technical field [0001] The present invention relates to a convolutional code decoding technology in the communication field, and more specifically, to a Viterbi decoder and a Viterbi decoding method. Background technique [0002] Convolution code (convolution code) is a kind of channel coding technology. Compared with block codes, convolutional codes maintain the memory effect of the channel. Convolutional codes encode k information bits into n bits, but k and n are usually very small, and are especially suitable for serial transmission with low delay. Different from the block code, the n code elements encoded by the convolutional code are not only related to the k pieces of information in the current segment, but also related to the previous N-1 segment information. The number of interrelated code elements in the encoding process is nN, and N is called the constraint length of the convolutional code. Convolutional code is a high-efficiency channel coding with excellent p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/41
Inventor 高波肖振宇金德鹏裴玉奎葛宁郭欣
Owner SONY CORP
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