A strained Si vertical back-channel nano-CMOS integrated device and its preparation method

A vertical channel and integrated device technology, which is applied in semiconductor/solid-state device manufacturing, nanotechnology, nanotechnology, etc., can solve the problems of increasing the difficulty of process manufacturing and limited adjustment range of device threshold voltage, so as to increase integration and improve Current drive capability, cost reduction effect

Inactive Publication Date: 2016-01-20
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method has a limited range of adjustment to the threshold voltage of the device, and also increases the difficulty of process manufacturing, making it a process bottleneck.

Method used

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  • A strained Si vertical back-channel nano-CMOS integrated device and its preparation method
  • A strained Si vertical back-channel nano-CMOS integrated device and its preparation method
  • A strained Si vertical back-channel nano-CMOS integrated device and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Embodiment 1: the strained Si back-type channel CMOS integrated device and circuit that the preparation conduction channel is 45nm, concrete steps are as follows:

[0054] Step 1, isolation preparation of MOS active region, such as figure 2 , image 3 shown.

[0055] (1a) Select the doping concentration to be 5×10 15 cm -3 An N-type Si substrate sheet 1;

[0056] (1b) using a dry etching process to etch a deep groove with a depth of 3.5 μm in the isolation region;

[0057] (1c) Deposit the first SiO with a thickness of 20 nm on the surface of the substrate at 600 ° C by chemical vapor deposition (CVD) method 2 Layer 2, covering all the inner surface of the deep groove;

[0058] (1d) Deposit a SiN layer 3 with a thickness of 50 nm in the deep groove at 600° C. by chemical vapor deposition (CVD);

[0059] (1e) Deposit SiO in deep trenches at 600 °C by chemical vapor deposition (CVD) 2 4. Form deep trench isolation 5.

[0060] Step 2, PMOS active region epitaxial...

Embodiment 2

[0099] Embodiment 2: the preparation of the strained Si back-type structure CMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:

[0100] Step 1, isolation preparation of MOS active region, such as figure 2 , image 3 shown.

[0101] (1a) Select the doping concentration as 3×10 15 cm -3 An N-type Si substrate sheet 1;

[0102] (1b) using a dry etching process to etch a deep groove with a depth of 3 μm in the isolation region;

[0103] (1c) Deposit the first SiO with a thickness of 30nm on the surface of the substrate at 700°C by chemical vapor deposition (CVD) 2 Layer 2, covering all the inner surface of the deep groove;

[0104] (1d) Deposit a SiN layer 3 with a thickness of 80 nm in the deep trench at 700° C. by chemical vapor deposition (CVD);

[0105] (1e) Deposit SiO in deep trenches at 700 °C by chemical vapor deposition (CVD) 2 4. Form deep trench isolation 5.

[0106] Step 2, PMOS active region epitaxial mat...

Embodiment 3

[0145] Embodiment 3: prepare the strained Si back-type structure CMOS integrated device and the circuit that the conductive channel is 22nm, the specific steps are as follows:

[0146] Step 1, isolation preparation of MOS active region, such as figure 2 , image 3 shown.

[0147] (1a) Select the doping concentration as 1×10 15 cm -3 An N-type Si substrate sheet 1;

[0148] (1b) using a dry etching process to etch a deep groove with a depth of 2.5 μm in the isolation region;

[0149] (1c) Deposit the first SiO with a thickness of 40 nm on the surface of the substrate at 800 ° C by chemical vapor deposition (CVD) method 2 Layer 2, covering all the inner surface of the deep groove;

[0150] (1d) Deposit a SiN layer 3 with a thickness of 100 nm in the deep trench at 800° C. by chemical vapor deposition (CVD);

[0151] (1e) Deposit SiO in deep trenches at 800 °C by chemical vapor deposition (CVD) 2 4. Form deep trench isolation 5.

[0152] Step 2, PMOS active region epita...

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Abstract

The invention discloses a nano CMOS (Complementary Metal-Oxide-Semiconductor) integrated device with a strain Si vertical clip-shaped channel and a preparation method of the device. The preparation method comprises the steps of firstly, preparing an active region on a substrate for isolation at 600 DEG C-800 DEG C, respectively and continuously growing a Si buffer layer, a gradual-change SiGe layer, a fixed component SiGe layer, a strain Si layer, a Si buffer layer, a gradual change SiGe layer, strain Si, fixed component SiGe layer, a light-doped source drain layer, a strain Si layer, a light-doped source drain (LDD) layer and a fixed component SiGe layer on an NMOS (N-channel Metal Oxide Semiconductor) active region and a PMOS (P-channel Metal Oxide Semiconductor) active region; respectively conducting dry etching on a drain channel and a grate channel on the PMOS active region, preparing drain regions and grate electrodes in the channels to form an NMOS device; and conducting photoetching on a lead wire to form a drain metal lead wire, a source metal lead wire and a grate metal lead wire so as to manufacture the CMOS integrated device and a circuit. According to the nano CMOS integrated device and the preparation method, the characteristic of anisotropism of the mobility rate of tensile strain Si material is utilized, the CMOS integrated device with the strain Si clip-shaped vertical channel and a circuit are manufactured under low temperature by the technology of the combination of a vertical structure and a horizontal structure, wherein the performance of the CMOS integrated device with the strain Si clip-shaped vertical channel is enhanced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a strained Si vertical back channel nanometer CMOS integrated device and a preparation method. Background technique [0002] At present, the electronic information industry with integrated circuits as the core has surpassed the traditional industries represented by automobiles, petroleum, and steel to become the largest industry, and has become a powerful engine and solid foundation for transforming and pulling traditional industries into the digital age. 65% of the growth of the national economic output value of developed countries is related to integrated circuits; integrated circuits in the US defense budget have already accounted for half of the country. It is estimated that in the next 10 years, the sales of integrated circuits in the world will grow at an average annual rate of 15%, and will reach 1 trillion US dollars in 2011. As the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L21/8238B82Y10/00
Inventor 胡辉勇宣荣喜张鹤鸣宋建军王斌王海栋李妤晨郝跃
Owner XIDIAN UNIV
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