Address mapping method for large memory devices of Loongson 3A platforms

Abstract

The invention discloses an address mapping method for large memory devices of Loongson 3A platforms, which comprises the implementation steps: 1) aiming at each CPU (central processing unit) core of a Loongson 3A processor, moving a PCI (peripheral component interconnect) memory space in a CPU address space out of an address range of a system register, and adjusting the size of the PCI memory space; 2) establishing a mapping relation between the PCI memory space being moved in the CPU address space and a memory space in a global address space, and establishing a mapping relation between the memory space in the global address space and a memory space in an HT (hyper transport) address space; and 3) according to the PCI memory space being moved in the CPU address space, updating a PCI memory resource structure body of an operating system. According to the invention, the large memory PCI / PCIE (peripheral component interconnect express) device support of a Loongson 3A platform can be realized, the popularization and application of the Loongson 3A platform can be promoted, and the method has the advantages of good compatibility and wide application range.

Description

technical field [0001] The invention relates to the field of computers using Loongson processors, in particular to an address mapping method for a Loongson 3A platform large memory device. Background technique [0002] The Loongson 3A processor is a general-purpose 64-bit processor developed by the Institute of Computing Technology, Chinese Academy of Sciences and compatible with the MIPS instruction set. Such as figure 1 As shown, the Loongson 3A processor adopts a multi-core processor architecture, and 4 CPU cores are integrated inside the chip. The overall architecture of the Loongson 3A processor chip is based on two-level interconnection: the first-level internal interconnection uses a 6x6 first-level crossbar switch, and the first-level crossbar switch is used to implement four CPU cores (core 0 to core 3), four Interconnect between the L2 cache and the two HT controllers. The second-level internal interconnection adopts a 5x4 two-level crossbar switch, and the two-...

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Problems solved by technology

In this way, these PCI / PCIE devices with large memory will fail during the initialization process, so they cannot run normally on the Loongson 3A platform, which ultimately affects the normal operation of the system and limits the industrial promotion and application of the Loongson 3A platform

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