The static power consumption elimination circuit of the chip input pull-up resistor
A technology of static power consumption and circuit elimination, applied in electrical components, electronic switches, pulse technology, etc., can solve the problem of large power consumption and achieve the effect of eliminating DC current
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[0014] Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0015] Such as figure 1 As shown, the static power consumption elimination circuit of the pull-up resistor at the input end of the chip includes an NMOS tube and a resistor R, and the NMOS tube and the resistor R are connected in series to the internal power supply V of the chip. cc1 Between the NMOS transistor and the input port P of the chip, the gate of the NMOS transistor is connected to the output end of a control circuit, and the input port of the chip is connected to one or more input ends of the control circuit, thereby forming a closed-loop circuit structure. The control circuit includes an RS flip-flop and an inverter 3, the RS flip-flop is composed of a first NAND gate 1 and a second NAND gate 2, the first NAND gate 1 is a three-terminal input NAND gate, and the second NAND gate NAND gate 2 is a two-terminal input NAND gate, and t...
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