I/O (input/output)pin allotting method for nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure

A technology of circuit structure and distribution method, applied in circuits, electrical components, electrical digital data processing, etc., can solve the problems of serious wiring crosstalk, soaring manufacturing costs, and sharply increasing difficulty in line width, etc., to expand the scope of connectivity, speed up Allocated time, the effect of speeding up allocating time

Inactive Publication Date: 2012-08-22
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the further narrowing of the line width of integrated circuits, silicon-based microelectronics technology will encounter many insurmountable challenges: (1) The difficulty of controlling line width through photolithography has increased sharply, which has far exceeded the current manufacturing level, making the development of corresponding Tool manufacturing costs skyrocket
(2) The quantum effect makes the crosstalk between the wires increasingly serious, hindering the integrity of the signal
However, the I / O pins are located at the outermost periphery of the CMOL circuit structure, and the actual connected domain size cannot reach or even be much smaller than the theoretical value, such as image 3 Example CMOL cell B shown, Λ(B)=(c 11 , c 12 , c 13 }

Method used

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  • I/O (input/output)pin allotting method for nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure
  • I/O (input/output)pin allotting method for nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure
  • I/O (input/output)pin allotting method for nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] Embodiment one: step 1.: define the circuit netlist and include I / O pin, logic gate unit and interconnection line, take as Image 6 The shown netlist based on the input circuit of the NOR gate, save the I pin and the O pin in the netlist of the input circuit into the set Q and W respectively, and the total number of I / O pins is n=| Q|+|W|, then Q=(i 1 , i 2 , i 3 , i 4 ), W={o}, the total number of I / O pins is n=|Q|+|W|=4+1=5, the logic gate unit in the input circuit netlist is saved in the set G, Then G=(1, 2, 3, 4, 5, 6, 7, 8, 9), the number of logic gate units is m=|G|=9;

[0040] Step ②: Define the nano-CMOS circuit structure as a two-dimensional cell array Ψ={c 0 , c 1 , c 2 , c 3 …c m-1}, its size is x*y, the horizontal coordinate is x, the vertical coordinate is y, where c i It is a nano-CMOS unit, that is, the number of nano-CMOS units m=x*y, i∈[0, m-1]; the outermost nano-CMOS unit of the two-dimensional cell array is the I / O pin allocation area, and ...

Embodiment 2

[0045] Step ①: Define the circuit netlist including I / O pins, logic gate units and interconnection lines, such as Figure 9 Shown based on the netlist of the input circuit of NOR gate, the I pin and the O pin in this input circuit netlist are saved respectively in the collection Q, among W, then Q={i 1 , i 2 , i 3 , i 4}, W={o}, the total number of I / O pins is n=|Q|+|W|=4+1=5. Save the logic gate units in the input circuit netlist into the set G, G={1, 2, 3, 4, 5, 6, 7}, the number of logic gates is m=|G|=7;

[0046] Step ②: Define the nano-CMOS circuit structure as a two-dimensional cell array Ψ={c 0 , c 1 , c 2 , c 3 …c m-1}, its size is x*y, the horizontal coordinate is x, the vertical coordinate is y, where c i It is a nano-CMOS unit, that is, the number of nano-CMOS units m=x*y, i∈[0, m-1]; the outermost nano-CMOS unit of the two-dimensional cell array is the I / O pin allocation area, and the two-dimensional All the other nanometer CMOS cells of cell array are lo...

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Abstract

The invention discloses an I / O (input / output)pin allotting method for a nano CMOS (Complementary Metal-Oxide-Semiconductor Transistor) circuit structure; the method provided by the invention has the advantages of capable of effectively solving the limited I / O pin allotting communication area of the nano CMOS circuit structure, and reducing complexity of the whole circuit. The method comprises thefollowing steps: a fan-out degree of an input pin I is analyzed, when the fan-out degree is larger than one threshold value Dout(T), the communication area is expanded by logically copying; a fan-in degree of an output pin O is analyzed, when the fan-in degree is larger than one threshold value Din(T), the communication area is expanded by inserting a pair of inverter sets so as to ease the allotting difficulty caused by high fan-out / fan-in of the I / O pin in the circuit. The test proves that the method provided by the invention can effectively solve the problem of difficultly allotting the I / O pin of the nano CMOS circuit structure.

Description

technical field [0001] The invention relates to an automatic design method for a nanometer CMOS circuit structure, in particular to an I / O pin assignment method for a nanometer CMOS circuit structure. Background technique [0002] At present, the large-scale production technology of silicon-based integrated circuits has reached a process of 0.09-0.065 microns, and will further reach 0.045 microns or even reach nanoscale. With the further narrowing of the line width of integrated circuits, silicon-based microelectronics technology will encounter many insurmountable challenges: (1) The difficulty of controlling line width through photolithography has increased sharply, which has far exceeded the current manufacturing level, making the development of corresponding The cost of manufacturing tools skyrocketed. (2) The quantum effect makes the crosstalk between the wires increasingly serious, hindering the integrity of the signal. For these reasons, silicon-based microelectronic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50H01L21/60
Inventor 夏银水储著飞王伦耀
Owner NINGBO UNIV
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