Design method and design device for cascade filter

Abstract

The embodiment of the invention provides a design method for a cascade filter, which comprises the following steps of: determining the interpolation times N of the filter; calculating the filter coefficient of a programmable finite impulse response (PFIR) filter, and obtaining a design scheme of a cascade combined filter of PFIR and cascaded integrator comb (CIC) filters; and when the interpolation times of the cascade combined filter of the PFIR and CIC filters does not reach the predetermined times, designing a half band (HB) filter, so that the filter performance of the cascade combined filter of the PFIR and CIC filters and the HB filter meets the interpolation times requirement of a system, and the design of the PFIR filter is realized by adopting a multistage design scheme. According to the embodiment provided by the invention, by adopting the design device for the multistage filter, the order of the designed filter is in a realizable range of the FPGA, and the indexes such as interpolation times of signals, error vector magnitude (EVM), adjacent channel power ratio (ACPR) and the like can meet the protocol requirement. Moreover, according to the technical scheme provided by the invention, the resource consumption of the filter is also lower than that of the design method for the traditional filter, and the use of FPGA hardware resources can be effectively reduced.

Description

technical field [0001] The present invention relates to the field of digital communication, in particular, the present invention relates to a design method and design device of a cascaded filter. Background technique [0002] In the field of digital communication, digital filters are usually used to improve communication quality. Filter design indicators mainly include transition bandwidth and sidelobe amplitude. The design of the filter usually hopes to obtain as narrow a transition band as possible and a lower side lobe amplitude. However, reducing the transition band and suppressing the side lobe amplitude cannot be achieved at the same time. Usually, the transition bandwidth is increased in exchange for side lobe suppression. For example, the sidelobe amplitude can be suppressed by adding a window function, but at the same time, the transition bandwidth is increased. In order to reduce the transition bandwidth, the order of the filter needs to be increased. Therefore, i...

AI Technical Summary

Problems solved by technology

This method is relatively random, and it is difficult to design filter coefficients with strict spectrum templates, such as strictly designing the root-raised cosine filter of TD-SCDMA

[0009] In the prior art, it is difficult to realize the carrier spacing of 1.4MHZ on the FPGA, and it is also difficult to design the filter coefficients of 1.4MHZ. Therefore, it is necessary to propose a technical solution to design a reasonable 1.4MHZ carrier spacing filter, so that 1.4MHZ carrier spacing filter design can be applied in the product

Images