Method for realizing microprogrammed control unit (MCU) verification platform based on verification methodology of verification methodology manual (VMM)
A verification methodology and verification platform technology, applied in the verification test field of 8-bit MCU, can solve problems such as low efficiency, lack of quantitative indicators, and verification quality cannot be guaranteed, and achieve the effect of saving verification time
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[0018] With SystemVerilog becoming the P1800 specification of the IEEE (Institute of Electrical and Electronics Engineers), more and more projects have begun to adopt SystemVerilog-based verification methodologies to obtain more reuse scalability, more comprehensive functional coverage, and more reasonable Hierarchical validation structure.
[0019] As the complexity of the design continues to increase, more resources need to be put into the verification. Not only the verification is required to cover all functions, but also a large number of abnormal conditions are expected to check the abnormal processing status of the module to be verified. Under traditional testing methods, the above requirements are often difficult to achieve. In addition, the design is constantly reused, and the verification also hopes to reuse similar verification modules, which leads to a hierarchical verification method. VMM verification methodology provides a verification method based on SystemVeril...
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