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Chip erasing method

A chip and word line technology, applied in the field of chip erasing in flash memory devices, can solve problems such as high power consumption, achieve the effects of reduced instantaneous power consumption, balanced decoding effect, and easy operation

Active Publication Date: 2011-02-02
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem solved by the present invention is to provide a chip erasing method to solve the instantaneous high power consumption and subsequent problems that may be caused when performing chip erasing operations

Method used

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Embodiment approach

[0020] refer to image 3 , an implementation manner of the chip erasing method of the present invention may include:

[0021] Step S1, obtaining the corresponding word line through decoding;

[0022] Step S2, dividing the corresponding word lines obtained by decoding into predetermined parts, and sequentially selecting the word lines of each part;

[0023] In step S3, after the decoding of all word lines is completed, a chip erasing operation is performed.

[0024] Wherein, the decoding method adopted in step S1 can be a bit-by-bit decoding mode, for example, according to the value of each word bit to determine the corresponding word line, for the 8-bit bit line (respectively a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) decoder, its decoding result can correspond to 2 8 word lines, wherein the value of the bit line of the decoder corresponding to the decoding result of the 35th word line is 00100011. In addition, the decoding in step S1 may also include other decoding methods,...

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Abstract

The invention relates to a chip erasing method, comprising the following steps: obtaining a corresponding word line through decoding, dividing the corresponding word line obtained by decoding into predetermined parts, respectively choosing the word lines from the parts, and performing chip erasing operation for all the chosen word lines. In the invention, the word lines are decoded and chosen in parts, which avoids large power consumption and reduces the influence on power supply voltage at the instant moment of simultaneously decoding and choosing the word lines, thus effectively realizing chip erasing action.

Description

technical field [0001] The invention relates to a flash memory device, especially a chip erasing method in the flash memory device. Background technique [0002] Flash memory (Flash Memory) is a non-volatile memory, which can still maintain the stored data information in the case of power failure. Flash memory is a variant of electronically erasable read-only memory (EEPROM). Unlike EEPROM, which can only be deleted and rewritten at the byte level, flash memory can perform erasing and writing of the entire chip, thus having a faster speed than EEPROM. [0003] Chip erase (chip erase) is an important operation in flash memory. In the prior art, such chip erasing method is usually adopted: first, decode all word lines in the chip to obtain the addresses of all word lines; then, select all word lines at the same time according to the decoding result; then, The selected word lines are set at the same time, for example, they are uniformly set to a high level or a low level, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/16G11C16/10
Inventor 杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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