Image processing method and device thereof for achieving seamless splicing large screen display
An image processing device and seamless splicing technology, applied in image communication, static indicators, cathode ray tube indicators, etc., can solve problems such as difficult light penetration, pixel loss, and inability to eliminate the influence of physical connection seams. , to achieve good display effect, prevent loss, and natural and smooth image transition
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Embodiment 1
[0038] In this embodiment, the splicing large screen is a splicing method composed of two display units in the horizontal direction, using one circuit for image data input, and two output circuits for image data output.
[0039] See image 3 As shown, it is a schematic diagram of a hardware structure for realizing seamless splicing large-screen display in this embodiment, which includes an access module (one access circuit), a storage module, an image segmentation processing module, an image brightness adjustment module, and an output module (output circuit A, output circuit B), display module (display unit A, display unit B).
[0040] In this embodiment, the functions of the storage module, the image segmentation processing module, and the image brightness adjustment module can be realized by using FPGA (Field Programmable Gate Array, element programmable logic gate array).
[0041] Realization, wherein the storage module can be a double-chain SRAM (Static Random Access Memo...
Embodiment 2
[0058] In this embodiment, the splicing large screen is a splicing method composed of 2×2 display units. In order to avoid the blank screen of some display units due to the image acquisition speed not keeping up with the display requirements, the two displays in the first row in the horizontal direction The unit uses one access circuit A to connect to the graphics card A for image input, and the two display units in the second row in the horizontal direction use one access circuit B to connect to the graphics card B for image input.
[0059] In this embodiment, a graphics card corresponds to a row of display units, and the output image of each graphics card is processed by an FPGA and an external memory, and the two FPGAs are connected through a synchronous signal to ensure that the upper and lower rows of display units are displayed synchronously. In this embodiment, the capacity of the external memory is the size for storing 2 lines of image data.
[0060] Except for the abo...
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Abstract
Description
Claims
Application Information
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