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Structure with compatibility of I2C and system management buses and time sequence buffering mechanism

A system management bus and buffer device technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problem of inconsistent data retention time, and achieve the effect of overcoming the interference of load capacitance and signal reflection.

Inactive Publication Date: 2009-05-13
武桂英
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  • Abstract
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Problems solved by technology

[0004] The present invention provides a framework compatible with the I2C bus and the system management bus to solve the disadvantage of inconsistent data retention time between the I2C bus and the system management bus in the prior art

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  • Structure with compatibility of I2C and system management buses and time sequence buffering mechanism
  • Structure with compatibility of I2C and system management buses and time sequence buffering mechanism
  • Structure with compatibility of I2C and system management buses and time sequence buffering mechanism

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Embodiment Construction

[0014] Please refer to FIG. 1 , which is a structural diagram of a compatible I2C bus and a system management bus according to an embodiment of the present invention.

[0015] The architecture 100 of the present invention compatible with the I2C bus and the system management bus includes a first device 101 , a second device 105 and a timing buffer device 109 . The first device 101 has an I2C bus interface 103 . The second device 105 has a system management bus interface 107 . The timing buffer device 109 is connected between the I2C bus interface 103 and the system management bus interface 107, and is used to make The data line on the system management bus interface 107 keeps the first state for a hold time and then changes to the second state, or makes the data line on the system management bus interface 107 change from the first state to the second state and then keeps the second state for one hold time. That is, because the I2C bus used by the first device 101 requires a...

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Abstract

The invention discloses an architecture compatible with an I2C bus and a system management bus. The architecture comprises a first device with an I2C bus interface, a second device with a system management bus interface and a time sequence buffer device which is connected between the I2C bus interface and the system management bus interface, and the time sequence buffer device can provide a time delay during the data transmission of the first device and the second device to meet the demand of the second device for the data retention time.

Description

technical field [0001] The present invention relates to a compatible bus architecture, and more particularly to a compatible I2C bus and system management bus architecture. Background technique [0002] In computer network communication equipment, the I2C bus (INTER-IC Bus or IC TO Bus) is often used. The I2C bus is a two-wire serial bus that works in master / slave mode. The two-line communication signal lines are respectively a serial clock line (SCL, Serial Clock Line) and a serial data (SDA, Serial Data) line. The I2C bus speed is from 0Hz to 3.4MHz. The I2C bus allows multiple devices to work on the same bus, and the master device (Master) uses the same clock for transmission. Since the I2C bus has only two wires, the slave device (Slave) only needs to be connected to the bus without additional logic. The system management bus (SM Bus for short) is mostly based on the I2C bus specification. The system management bus is also a two-wire serial bus. The system management ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 邹小兵刘士豪
Owner 武桂英
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