Method and circuit for loading on site programmable gate array

Abstract

The invention provides a loaded circuit for a field programmable gate array and a loading method thereof. The loaded circuit comprises a microprocessor, a nonvolatile memory and the field programmable gate array, wherein the nonvolatile memory is connected with the microprocessor, and the microprocessor is connected with the field programmable gate array. When the loaded circuit is used to load data, the microprocessor reads and loads data from the nonvolatile memory and writes the loaded data in a register; and the loaded data is read from the register by a controller and is transmitted to the field programmable gate array through a loaded digital signal. The loaded circuit can improve the speed of the whole loading process and greatly reduce the loading time, thereby reducing the system starting and configuration time and the system fault recovery time, and improving the product performance and indexes.

Description

technical field [0001] The invention relates to a method for loading files into a field programmable gate array and a corresponding loading circuit. Background technique [0002] FPGA (Field-programmable gate arrays, Field Programmable Gate Array) is an erasable and programmable read-only memory. Usually, when the board is powered on and initialized, relevant program data is loaded into the FPGA. After the FPGA is initialized, it can complete complex logic control and realize various business processing functions. Since the FPGA is a logic chip that does not save data after power-off, it is required to reload after each power-on, that is, to reload the program data and write it into the FPGA chip so that it can work normally. [0003] See figure 1 , figure 1 It is a kind of existing loading circuit to FPGA loading file, and this circuit comprises microprocessor (MCU) 11, non-volatile memory DATAFLASH 12 and FPGA 13, and non-volatile memory 12 is connected with MCU 11, an...

AI Technical Summary

Problems solved by technology

[0008] Since this loading method needs to control the working status of each pin through software, the software control method usually has an upper limit threshold for the highest transmission rate, so the data loading speed is limited. At the same time, the control time of GPIO pins is limited by the MCU. For example, loading data uses software to control the ARM instruction clock and data transmission of the digital board. The loading time of the FPGA is limited by the instruction clock of the MCU, and the ARM instruction clock of the digital board usually controls the clock for loading the FPGA to about 500K

Moreover, to load a byte of data, you need to control the CCLK and D_IN pins eight times respectively. For FPGA data that loads large files, the loading time is difficult to control, and even the loading time is too long, which affects the system initialization.

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