Heterogeneous multi-core system based on configurable processor and instruction set extension

Abstract

The present invention discloses a heterogeneous multi-nuclear system based on configurable processor and instruction set extension pertaining to the computer system technique field, including extension nucleus, a fundamental nuclear or an almightiness nuclear, wherein the fundamental nuclear includes a basic instruction set ISA1, for implementing the part that has not executed the instruction extension optimization in the operating system and the application program and being responsible for communicating control between nucleus, when the extension nuclear communicates with the fundamental nuclear, the FIFO is required to apply for open, the communication channels can be established after the fundamental nuclear authorizes the application. The extension nuclear contains a basic instruction set ISA1 and an extension instruction set, principally for the implementation of the part that has executed the instruction extension optimization in the application program, and also for the implementation of the part that has not executed the instruction extension optimization in the application program. The almightiness nuclear includes all the instruction set, which has functions of the fundamental nuclear and all the extension nucleus. The present invention has largely exerted the advantage of the extension instruction, simultaneously alleviates the burden on the fundamental nuclear, and effectively resolves the problem that the multithreading application program has low implementing efficiency.

Description

technical field [0001] The invention relates to a system structure in the technical field of computer systems, in particular to a heterogeneous multi-core system based on a configurable processor and instruction set expansion. Background technique [0002] In recent years, the design of high-performance multiprocessors has begun to occupy an increasingly important position in the architecture. The emergence of multi-processor architecture reduces the requirement for instruction-level parallelism, and replaces it with the research on thread-level parallelism. This shift of research focus is mainly due to the complexity of uniprocessor parallel design and the huge difference between processor speed and memory access speed. For a multi-processor system, the structure of each core can be simplified to enhance the multi-thread processing capability. [0003] In the isomorphic structure, each processor is indifferent, which is more suitable for general and repetitive application...

AI Technical Summary

Problems solved by technology

[0006] Aiming at the deficiencies of the prior art, the present invention proposes a heterogeneous multi-core system based on configurable processors and instruction set extensions to solve the problem of low execution efficiency of multi-threaded applications with large differences between threads

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