Duo-binary system CTC code translator

A decoding device, duobinary technology, applied in the direction of error correction/error detection using convolutional codes, error correction/error detection by combining multiple code structures, data representation error detection/correction, etc., can solve problems that are not suitable for hardware Realization and other issues

Inactive Publication Date: 2010-02-10
ZTE CORP +1
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  • Description
  • Claims
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Problems solved by technology

[0018] But this algorithm is still not suitable for direct hardware implementation

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  • Duo-binary system CTC code translator
  • Duo-binary system CTC code translator
  • Duo-binary system CTC code translator

Examples

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Embodiment Construction

[0145] like image 3 As shown, the embodiment of the CTC decoding device of the present invention includes an overall input FIFO module 31, an overall output FIFO module 32, an input scheduling module 33, an output scheduling module 34, a decoding data memory 35, a decoding core module output FIFO 36 and two Parallel cascaded decoding core module 1, namely: decoding core module 1 and decoding core module 2, wherein: overall input FIFO module 31, its main function is to complete the CTC decoding data packet received and sent; decoding data Memory 35, its main function is used to store decoding data, and each decoding core module has a dual-port RAM; Input scheduler module 33, its main function adopts fair round-robin scheduling method to schedule decoding data; Output scheduling Decoder module 34, its main function adopts fair round-robin scheduling method to schedule decoding data; Decoding output FIFO 136, its main function is to store the decoding result of decoding core mod...

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Abstract

The invention relates to a dual-binary CTC decoder, comprising a total input FIFO module (31)connected with an input, a total output FIFO module (32)connected with an output, a parallel cascade decodecore module (1)connected with the total input FIFO module via a decode data memory (35)on the input and connected with the total output FIFO module via a decode core module output FIFO (36)on the output, an input distribution module (33)for controlling the connection between the decode data memory and the total input FIFO module, and an output distributing module (34)for controlling the connection between the decode core module output FIFO and the total output FIFO module. The invention has expandable structure, which can increase decode core module number according to decode throughout, to realize high-speed decoding and meet IEEE standard.

Description

technical field [0001] The invention relates to the field of mobile communication, in particular to a duobinary CTC (convolution turbo code) decoding device. Background technique [0002] C.Berrou et al. in France proposed a coding scheme called Turbo code, which made people take a big step towards the limit of coding performance. Turbo code is a kind of concatenated code, which is formed by parallel concatenation of two convolutional codes. Each sub-encoder uses a feedback convolutional code encoder, and an interleaver is used between the sub-encoders to eliminate the correlation between sub-codes. At the same time, the decoding part of the Turbo code adopts the decoding algorithm of soft input and soft output and the method of iterative decoding, so that the sub-decoders can transfer information to each other and ensure the full utilization of the encoded information. The more irrelevant the two encoding output sequences are, the greater the amount of information exchang...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/29H03M13/23
Inventor 王锦山
Owner ZTE CORP
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