Chip algorithm simulating platform and method

Abstract

The invention discloses an artificial platform and method of chip algorithm, which comprises the following parts: system container base, artificial control unit, placing unit, connecting unit and operating unit, wherein the system container base stores at least one system container to realize present algorithm; the placing unit sends the needed system container in the system container base to the artificial control unit, which forms algorithm artificial model according to the connection relationship of all system containers in the artificial control unit through connecting unit; the artificial control unit sends the model to the operating unit, which execute the artificial operation and generates operating result. The invention improves the quality of algorithm artificial model, which lessens the burden of chip designer.

Description

Technical field [0001] The invention relates to chip algorithm design, in particular to a chip algorithm simulation platform and method. Background technique [0002] At present, chips are playing an extremely important role in many industries and fields such as communications, computers, intelligent systems, automatic control, and space technology, and promote the development of informatization of the entire society. In general, chip production includes two stages: chip design and chip manufacturing. Due to the high cost of chip manufacturing, the specific manifestation is that it costs hundreds of thousands of dollars each time to roll out the chip, and once the chip is taped out, the internal logic structure of the chip cannot be changed. Therefore, before the chip is manufactured, careful and careful chips are required. Design work. [0003] The so-called chip design refers to content such as algorithm implementation and peripheral logic circuit design. Among them, the algori...

AI Technical Summary

Problems solved by technology

That is to say, all the simulation software currently running on the computer use the interpretation method to execute the hardware description language, so the execution speed is very slow, which greatly restricts the error checking speed of the chip algorithm, and cannot meet the debugging and analysis requirements of the algorithm simulation model

For example, using the V568 algorithm simulation model built on the existing simulation platform, it takes more than one day to generate a simple VGA image

[0006] 2. It takes up a lot of resources

[0007] 3. The system is complex

[0008] 4. Difficulty in debugging

After locating the error of the algorithm simulation model, the hardware design engineer needs to modify the code and re-simulate, which will increase the complexity of the Debug process and lead to a large number of pseudocodes in the hardware code

Images