Memory management methods and systems that support cache consistency

Abstract

Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Embodiments of the present invention relate to computer system memory, in particular the management of cache memory.[0003]2. Related Art[0004]With direct memory access (DMA), an input / output (I / O) system can issue read requests and writes directly to main memory without passing through the central processing unit (CPU). However, if the I / O system uses DMA to write to main memory, and changes data cached previously by the CPU, then the CPU will not receive the new data unless the CPU fetches the data from main memory. Also, for DMA reads, the CPU cache may contain more recent data than main memory, and so the I / O system will not receive the new data unless it reads the cache instead of main memory. Multiprocessor systems, particularly systems referred to as shared-memory simultaneous multiprocessor (SMP) architectures, have to deal with similar types of scenarios. The MESI (Modified, Exclusive, Shared, Invalid) protocol ...

AI Technical Summary

Benefits of technology

"The present invention provides a method or system for maintaining sequential consistency in a lumped architecture, which allows multiple memory operations to be included in an instruction group. The method includes executing a group of instructions that includes a cache line access instruction, updating an indicator to indicate that the cache line has been accessed, and rolling back and reissuing the instruction group if an external agent snoops the cache and the cache line is indicated as having been accessed. This allows for more efficient processing and better performance in a computer system."

Problems solved by technology

Prior attempts to achieve a sequentially consistent, lumped architecture are limited with respect to the number of memory operations that can be included in an instruction group.

Specifically, such attempts are limited to a single memory operation per instruction group.

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