Method for manufacturing stacked package structure

Abstract

A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part of U.S. application Ser. No. 11 / 409,933, filed on Apr. 24, 2006, hereby incorporated by reference as it fully set forth herein.FIELD OF THE INVENTION [0002] The present invention relates to a system-in-package (SiP) structure and a method for manufacturing the same, and more particularly, to a stacked package structure and a method for manufacturing the same. BACKGROUND OF THE INVENTION [0003] The demand for low cost, small size, and more functionality has become the main driving force in the electronic industry. To achieve such goals, advanced packaging techniques like flip chip, chip scale package, wafer level packaging, and 3D packages have been developed. The 3D packaging technique is developed to integrate dies, packages and passive components into one package, in other words, to achieve system in a package solution. The integration can be made in side-by-side, stacked, or both manners. Th...

AI Technical Summary

Benefits of technology

[0008] Therefore, one objective of the present invention is to provide a method for manufacturing a stacked package structure, which can reduce the area occupied by the package structure to greatly decrease the area of a printed circuit board.

[0009] Another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can integrate the connection between an upper chip package structure and a bottom chip package structure.

[0010] Still another objective of the present invention is to provide a method for manufacturing a stacked package structure, which can effectively avoid warpage from occurring in the connection of chip package structures, and prevent a cold joint condition from occurring between the chip package structures, so as to greatly enhance the yield of the stacked package structure.

Problems solved by technology

As a result, the reliability of the stacked package structure is seriously deteriorated, the yield of the package process is greatly reduced, and the cost is substantially increased.

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