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Carry-ripple adder

A bit-by-bit, adder technique used in instruments, a quantity counter, calculations using non-contact manufacturing equipment, etc.

Inactive Publication Date: 2006-03-15
INFINEON TECH AG
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this known structure is disadvantageous with regard to processing speed, and the substrate area required for implementation using complementary CMOS gates due to the resulting large number of transistors

Method used

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Examples

Experimental program
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Embodiment Construction

[0034] In the figures, like reference symbols designate identical or functionally identical components.

[0035] Figure 1 shows the principle of a "3 and 2 to 3 carry-wise adder" 10 with three bit inputs i0, i1 and i2, two identical carry inputs ci1, ci2, two identical carry outputs co1, co2 and a sum output s sexual description.

[0036] Figure 2 shows the truth or function table for a bit in the bit-wise carry adder in Figure 1. According to the code selected for the two identical carry-out signals co1 and co2, no combination of inputs where ci2 = 1 and ci1 = 0 (hatched in Figure 2) occurs in operation, because only if ci1 has been set Sets ci2, from which the double carry is deduced. The fact that "do not care elements" occur is used to minimize the circuit. A simple sum of the five input bits at the inputs i0, i1, i2, ci1, ci2 produces the table at position s, e.g. if the sum of the input bits ≥ 2, a carry is produced at the output co1, once the sum of the five input bi...

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Abstract

The present invention relates to a ripple adder (10), which comprises three first inputs (i0, i1, i2) used for providing three input bits (i0,i1,i2)for summation with the same significance bit 2; two second inputs(ci1,ci2)used for providing two jump / carry bits (ci1,ci2) with the same significance bit 2 for summation as well; output (s), used for outputting calculative sum bits(s_n)with the same significance bit 2; two outputs (co1,co2)used for outputting two calculative jump / carry bits (co1,co2)with the same significance bit 2 yet higher than the significance bit 2n of sum bits(s_n).

Description

technical field [0001] The present invention relates to bit-by-bit carry adders, more particularly to "3 and 2 to 3 bit-by-carry adders". Background technique [0002] As we all know, a bitwise carry adder is an adder with sequential carry logic. In a manner similar to carry-store adders, they have multiple inputs of the same significance, and the bits applied to these inputs are added during operation. The sum of bits is output at the output of the different significant digits, for example in the representation of a binary-coded number (binary-coded number BCD). [0003] To add multiple bits of the same significance, such as in a multiplier, it is common practice to build a carry-save adder, for example, according to the Wallace tree adder algorithm, and finally use a vector merge adder to combine the resultant sum with the redundant digit Hao represents the carry data converted to unambiguous number notation. This final stage is often in the form of a bit-wise adder, wh...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/50G06F7/509G06F7/53G06F7/60H04B
CPCG06F7/607G06F7/509G06F2207/3872G06F7/5318
Inventor 马克·贝纳尔若埃尔·哈彻温弗里德·坎普西格马尔·克佩
Owner INFINEON TECH AG
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