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Processor and method for trans-boundary aligned multiple transient memory data

A temporary register and cross-boundary technology, applied in the field of data processing, can solve the problems of processor pipeline stop, waste of bus bandwidth, etc.

Inactive Publication Date: 2005-06-01
SUNPLUS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

And because of repeated reading and writing to the same memory and scratchpad location, the possibility of a processor pipeline stall (Pipeline Stall) increases
Repeatedly reading the same memory location wastes bus bandwidth, especially in systems that do not have cache memory, causing delays that are even more pronounced

Method used

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  • Processor and method for trans-boundary aligned multiple transient memory data
  • Processor and method for trans-boundary aligned multiple transient memory data
  • Processor and method for trans-boundary aligned multiple transient memory data

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Embodiment Construction

[0035] FIG. 4 shows a block diagram of a processor utilizing cross-boundary aligned complex register data according to the present invention, which includes a decoding device 100 , a control device 200 , a register file 300 and a shifter 400 . The register file 300 has a plurality of registers 3001, and each register 3001 has N bits. In this embodiment, the value of N is preferably 32. The temporary register file 300 can read the temporary register 3001 according to a first address 301 and a second address 302 respectively, and output from a first output terminal 310 and a second output terminal 320, and can be output according to a The third address 303 is written into one of the multiple registers 3001 through an input terminal 330 (N is a positive integer).

[0036] The decoding device 100 decodes a multiple shift instruction, which can be divided into a multiple left shift instruction (Multiple Left Shin Instruction, MLSI) and a multiple right shift instruction (Multiple R...

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Abstract

The present invention proposes one kind of processor capable of aligning datan in several temporary storages across boundary and its method. There are one decoder for decoding multiple shift command; one temporary storage file with several temporary storages of N bits; one shifter to connect the first output content and the second output content in the temporary storage file serially to form one 2N bit word block, shift the 2N bit word block by w bits and output the first N bits; and one controller to set the temporary storage file according to the decoded multiple shift command, read out the content in corresponding temporary storage, and write the w bits shifted output of the shift into the temporary storage file.

Description

technical field [0001] The present invention relates to the technical field of data processing; in particular, it refers to a processor and method for utilizing data in multiple temporary registers that can be aligned across boundaries. Background technique [0002] When the processor performs data processing, the alignment of the data is related to the performance of many key operations, such as the performance of operations such as strings and arrays. As shown in Figure 1, a piece of data to be processed (ABCDEFGHIJKL) often crosses the data storage boundary. When a processor performs string or array operations on the data, it needs to perform many additional operations in order to be able to process the data. After the data is restored to an aligned format, the processor can perform related operations on the pen data. [0003] To deal with the problem of data misalignment, a known method is to load the data into the processor, and then use various processor instructions ...

Claims

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Application Information

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IPC IPC(8): G06F9/315
Inventor 梁伯嵩
Owner SUNPLUS TECH CO LTD
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