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Novel frequency divider

A frequency divider, a new type of technology, applied in pulse counters, counting chain pulse counters, pulse counters using semiconductor devices, etc., can solve the problems of high power consumption and large area, and achieve the effect of saving power consumption and area

Pending Publication Date: 2021-10-01
北京北斗华大科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This technical solution has the disadvantages of large power consumption and large area

Method used

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Examples

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Embodiment 1

[0015] Example 1: Please refer to figure 2 , the novel frequency divider of the embodiment of the present invention includes four three-input NOR gates with the same specifications. The four three-input NOR gates are connected in a ring, and the output end of the three-input NOR gate is connected to an input end of the next adjacent three-input NOR gate. The novel frequency divider of the embodiment of the present invention utilizes an externally provided clock signal to directly generate four different phase signals whose frequency is 1 / 2 of the input clock and whose duty cycle is 25%.

[0016] The present invention uses four identical three-input NOR gates (3-input NOR gate) to be connected in a ring, and utilizes an externally provided clock signal to directly generate four kinds of frequency which are 1 / 2 of the input clock and duty ratios are all 1 / 2. 25% different phase signals. The overall circuit architecture is as figure 2 shown. Each of the four NORs in this ri...

Embodiment 2

[0022] Embodiment 2: According to De Morgan's law, this structure can also be implemented with a three-input NAND gate (3-input NAND gate). For the actual circuit structure, please refer to Figure 4 , the novel frequency divider of the embodiment of the present invention includes four three-input NAND gates with the same specifications. The four three-input NAND gates are connected in a ring, and the output end of the three-input NAND gate is connected to one input end of the next adjacent three-input NAND gate. The novel frequency divider of the embodiment of the present invention utilizes the externally provided clock signal to directly generate four different phase signals whose frequency is 1 / 2 of the input clock and whose duty ratio is 75%. Different phase signals with a duty cycle of 25% can be obtained by using a phase converter.

[0023] As an implementation manner, the three-input NAND gate includes two MOSs connected in parallel.

[0024] Such as Figure 5 As sho...

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Abstract

The embodiment of the invention discloses a novel frequency divider which comprises four three-input NOR gates with the same specification, the four three-input NOR gates are annularly connected, and the output end of each three-input NOR gate is connected with one input end of the next adjacent three-input NOR gate. Only one-stage logic gate is needed, and compared with a common two-stage method that one frequency divider is needed and then a NAND gate or a NOR gate is used for synthesizing 25% duty ratio output, the power consumption and the region can be effectively saved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a novel frequency divider. Background technique [0002] Due to the popularity of current-mode passive mixers, their local oscillator signals generally require a signal with a duty cycle of 25%. At present, the most common way to generate this kind of local oscillation signal is the method proposed by the Journal of Solid-State Circuit "Analysis and optimization of direct-conversion receivers with 25% duty-cycle current-driven passive mixers" in 2010. Followed by a NAND gate (NOR gate is also available), such as figure 1 shown. This technical solution has the disadvantages of large power consumption and large area. Contents of the invention [0003] The technical problem to be solved by the embodiments of the present invention is to provide a novel frequency divider to reduce power consumption and area. [0004] In order to solve the above-mentioned technical pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/00H03K19/20
CPCH03K23/002H03K19/20
Inventor 陆熙良曾奕恩李拥平孙中亮曾奕棻
Owner 北京北斗华大科技有限公司
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