Successive approximation type analog-to-digital converter and three-level switching method thereof

Abstract

The invention discloses a successive approximation type analog-to-digital converter and a three-level switching method thereof. The method comprises the steps that input signals VIP and VIN are compared N times to obtain an N-bit digital code, the N-bit digital code is divided into a sampling stage and a conversion stage, and in the sampling stage, the input signals VIP and VIN are connected to top polar plates of an upper capacitor array and a lower capacitor array through sampling switches respectively, and the bottom polar plate of each capacitor is connected to a corresponding voltage; inthe conversion stage, the comparator performs MSB bit-to-LSB bit comparison on the voltages of the top electrode plates of the upper capacitor array and the lower capacitor array to obtain corresponding digital codes, and the connection relation of the capacitor bottom electrode plates in the capacitor arrays is controlled according to the digital codes; and comparing for N times is performed to obtain an N-bit digital code. According to the invention, the voltage change of + / -Vref is generated on the top plate of the capacitor for the first time, so that the reference voltage Vref of the capacitor array is reduced to half of the reference voltage Vref of a common method. Compared with a traditional switching algorithm, the method has the advantages that 99.79% of DAC power consumption isreduced, 75% of capacitance area is saved, common-mode level offset is only 0.5 LSB, and compromise of energy efficiency, area and common-mode level is achieved.

Description

technical field [0001] The invention relates to a successive approximation analog-to-digital converter and a three-level switching method thereof, belonging to the technical field of capacitive DAC of SARADC. Background technique [0002] In areas such as the Internet of Things and wearable devices, long-term sensors are required, and the sensor interface uses ADCs extremely frequently. Due to the requirement of service life, ADC needs to achieve low power consumption. Successive approximation analog-to-digital converters (SARADC) are widely used at low voltage due to their high degree of digitization and high energy efficiency. The commonly used SARADC structure includes sampling switches, CDACs, comparators, SAR logic and output circuits, and at low speeds, the switching power consumed by CDACs accounts for a large proportion of the overall power consumption. [0003] In the existing research, a variety of switching algorithms are proposed to reduce the switching power c...

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Problems solved by technology

However, they introduce reset power consumption, common-mode level shift [1], and multiple comparators [2] while reducing switching power consumption. In the end, either the reduction in DAC power consumption is not ideal, or for other modules, For example, the design index of the comparator puts forward higher requirements

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