2D scan tree structure for measurable scan design of low-power integrated circuits

A two-dimensional scanning, integrated circuit technology, applied in the direction of electronic circuit testing, circuits, electrical components, etc., can solve the problems of complex structure and low symmetry, and achieve the effect of large optimization space, reducing requirements and reducing interconnection complexity.

Inactive Publication Date: 2003-10-08
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Its disadvantage is that two sets of binary trees need to be constructed for sweeping in and sweeping out, and the structure is relatively complicated due to the low symmetry

Method used

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  • 2D scan tree structure for measurable scan design of low-power integrated circuits
  • 2D scan tree structure for measurable scan design of low-power integrated circuits
  • 2D scan tree structure for measurable scan design of low-power integrated circuits

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Experimental program
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Effect test

Embodiment 2

[0035] In the second embodiment, a two-dimensional L×H scan tree structure is formed by 1000 scan register units, wherein L=200, H=5, and the two-dimensional scan tree circuit used by each scan register unit SSF is the same as that in the first embodiment, such as image 3 shown.

Embodiment 3

[0036] In the third embodiment, a two-dimensional L×H scanning tree structure is formed by 5000 scanning register units, wherein L=1000 H=5. The two-dimensional scan tree circuit used by each scan register unit SSF is the same as that in the first embodiment, such as image 3 shown.

[0037] Table 1 shows the comparison of the bit pass rate between the above three embodiments and the traditional one-dimensional scan register structure.

Embodiment 1

[0038] Embodiment 1: The number of scan register units is N=500. If a one-dimensional scan chain is used, the bit pass rate (RBP1)=125250. When H=5, that is, H / N=1%, the bit pass rate (RBP2 )=6550, RBP1 / RBP2=19.12, that is to say, the power consumption of the circuit using the two-dimensional scanning structure is about 1 / 19 of that of the one-dimensional scanning circuit.

[0039] Implementation 2: The number of scan register units is N=1000, if a one-dimensional scan chain is used, its bit pass rate (RBP1)=500500, when H=5, that is to say H / N=0.5%, the bit pass rate (RBP2) =23100, RBP1 / RBP2=21.67, that is to say, the power consumption of the circuit using the two-dimensional scanning structure is about 1 / 21 of that of the one-dimensional scanning circuit.

[0040] Implementation 3: The number of scan register units is N=5000, if a one-dimensional scan chain is used, the bit pass rate (RBP1)=12502500, when H=10, that is to say H / N=0.2%, the bit pass rate (RBP2) =152750, RBP1...

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Abstract

A 2D scan tree structure for the measurable scan design of low-power IC includes scanning N registers. It features that a 2D array (LXH) composed of H groups of scan chain circuits and L groups of serial scan chain circuits is used to constitute a scan tree, where LXH=N. Its advantages are simple interconnection between registers, ability to constitute local scan chain as required, and low requirement to optimize timer tree.

Description

technical field [0001] The invention belongs to the technical field of testability design of digital electronic systems. In particular, it relates to testability scan design for integrated circuits and digital electronic systems. [0002] Its main feature is: transform the original one-dimensional structure of the testability design for scanning into a two-dimensional testability scanning circuit structure. The purpose of this is that as long as the designer reasonably selects the number of components in each dimension of the two-dimensional structure, the power consumption cost brought by the use of the scanning design method can be greatly reduced. This is because the adoption of the two-dimensional scanning structure can greatly reduce the overall bit pass rate (Rate of Bit Propagation-RBP) of the scan chain, thereby enabling it to reduce the power consumption of the overall circuit. Background technique [0003] The core of the so-called scan-based design for test tech...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G06F17/16H01L27/02
Inventor 孙义和徐磊陈弘毅
Owner TSINGHUA UNIV
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