Zero-overhead circulating device and implementation method, system and equipment and computer medium

Abstract

The invention discloses a zero-overhead circulating device and an implementation method, system and equipment and a computer medium. The method comprises the following steps: receiving an air circulation instruction sent by the RISC-V processor; analyzing a circulation initial value, a circulation step length, a circulation mode and a circulation ending condition in the empty circulation instruction; taking the cyclic initial value as a counting base value, and performing operation on the counting base value and the cyclic step length according to a cyclic mode to obtain a real-time counting value of the current round; judging whether the real-time count value of the current round meets a cycle ending condition or not, if not, updating the real-time count value into a counting base value,returning to the step of operating the counting base value and the cycle step length according to a cycle mode, and if yes, returning an empty cycle ending message to the RISC-V processor. According to the zero-overhead circulating device, the implementation method, system and equipment and the computer readable storage medium provided by the invention, performance of the RISC-V processor is improved.

Description

technical field [0001] The present application relates to the technical field of processors, and more specifically, relates to a zero-overhead cycle device and an implementation method, system, device, and computer medium. Background technique [0002] When the RISC-V processor processes the empty loop statement in the RISC-V instruction set, the keyword volatile is used to define the empty loop statement. After that, the compiler compiles the empty loop statement into an addition instruction and a jump branch instruction according to the keyword, thereby realizing the loop Effect. The RISC-V processor involved in this application refers to a processor running a RISC-V program. [0003] However, the addition instruction and the jump branch instruction will occupy the storage space of the RISC-V processor, which will reduce the performance of the RISC-V processor. [0004] To sum up, how to improve the performance of the RISC-V processor is an urgent problem to be solved by...

AI Technical Summary

Problems solved by technology

[0003] However, the addition instruction and the jump branch instruction will occupy the storage space of the RISC-V processor, which will reduce the performance of the RISC-V processor

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