Information flow tracking model generation method of a programmable logic device

Abstract

The invention relates to a high-precision information flow tracking model generation method. The method includes inputting programmable logic device codes; identifying instantiated module names in thecodes; matching the module name with a module name in a netlist library corresponding to the programmable logic device, if the module name is consistent with the module name in a netlist library corresponding to the programmable logic device, determining that the code is a gate level, otherwise, determining that the code is an RTL level, processing display flow in the RTL level, traversing all inputs, calculating assignment statement output, and converting a result into a truth table; inputting an original truth table by using a gate-level information flow theory, and generating a truth tableof full-input / output information flow stain labels; and using the Carnot graph simplified truth table to convert the truth table into information flow tracking logic, and processing implicit flow inthe RTL level, thereby realizing information flow processing of RTL level codes, and processing the gate-level hierarchical information flow. The RTL-level hierarchical codes and the gate-level hierarchical codes in the programmable logic device are classified and subjected to information flow tracking processing respectively, and a programmable logic device information flow tracking model is generated.

Description

technical field [0001] The invention relates to the field of integrated circuit safety detection, in particular to a method for generating an information flow tracing model of a programmable logic device. Background technique [0002] In programmable logic devices, there may be some security risks, including loopholes left unintentionally by designers or hardware Trojans implanted maliciously by attackers. Gate-level information flow technology is a technology that can capture all binary bit data flows in integrated circuit design, and can effectively detect loopholes or malicious codes in the design. At present, most gate-level information flow tracking technologies are aimed at ASIC design. Processing, the existing gate-level information flow technology to generate programmable logic device information flow tracking model has the following disadvantages: [0003] Applicability is poor. The existing gate-level information flow technology is aimed at ASIC design, using Des...

AI Technical Summary

Problems solved by technology

For the design of programmable logic devices, the combinational logic in the gate-level netlist is implemented by a look-up table (LUT), so the existing technology cannot be fully applicable to the design of programmable logic devices such as xlinx and altera

[0004] Inaccurate information flow

Since the traditional gate-level information flow technology cannot process LUT and other units in the netlist of programmable logic devices, these units can only be black-boxed for the generated information flow tracking model, so the accuracy of the generated information flow model is not high

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