Data converter and its control method for impedance matching

Abstract

The disclosure discloses a data converter and a control method for impedance matching thereof. The data converter includes a comparator, a capacitor array, a switch and an impedance matching circuit. The comparator has a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input end or the second input end. The switch and the impedance matching circuit are coupled to a second terminal of a target capacitor among the plurality of capacitors, the second terminal is coupled to a first reference voltage or a second reference voltage according to a control signal, and according to An impedance adjustment signal adjusts the impedance, wherein the impedance is the impedance of the switch and the impedance matching circuit. The first reference voltage is not equal to the second reference voltage.

Description

technical field [0001] The present disclosure relates to data converters, and more particularly, to impedance matching of data converters. Background technique [0002] figure 1 It is the circuit diagram of the existing single-stage comparator. The comparator 100 is mainly composed of a transistor 120 and a transistor 130 . When the comparator 100 switches from the reset state (switch 110 is turned on) to the comparison state (switch 110 is not turned on), the signals on the output terminal Vo- and the output terminal Vo+ will pass through the parasitic capacitance 125 of the transistor 120 and the transistor 130, respectively. The parasitic capacitance 135 of 100 kicks back to the negative (inverting input) Vi- and positive (non-inverting input) Vi+ of the comparator 100 , resulting in erroneous comparison results. [0003] Although the above-mentioned kickback noise will theoretically become a common mode component of the input signal for the two-stage comparator, when ...

AI Technical Summary

Problems solved by technology

When the comparator 100 switches from the reset state (the switch 110 is on) to the comparison state (the switch 110 is off), the signals on the output terminal Vo- and the output terminal Vo+ will pass through the parasitic capacitance 125 of the transistor 120 and the transistor 130 respectively. The parasitic capacitance 135 kicks back (kickback) to the negative pole (inverting input terminal) Vi- and the positive pole (non-inverting input terminal) Vi+ of the comparator 100, thereby causing wrong comparison results

[0003] Although the above-mentioned kickback noise (kickback noise) will theoretically become a common-mode component of the input signal to the two-stage comparator, when the equivalent impedance coupled to the negative and positive terminals of the comparator does not match, the comparator will still Can be affected by kickback noise

Images