A standard answer generation method for an on-line Verilog code automatic decision system

A standard answer and code technology, applied in code compilation, program code conversion, creation/generation of source code, etc., can solve problems such as systems without Verilog code judgment

Active Publication Date: 2018-12-28
HANGZHOU DIANZI UNIV
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Problems solved by technology

[0002] In the online education process of EDA (Electronic Design Automatic) course, the brand-new online education method of Verilog code judgment has been widely used; the key to realize the function of Verilog code judgment is to design and implement a A set of algorithms for Verilog code analysis, simulation and jud

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  • A standard answer generation method for an on-line Verilog code automatic decision system
  • A standard answer generation method for an on-line Verilog code automatic decision system

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[0025] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0026] On the contrary, the invention covers any alternatives, modifications, equivalent methods and schemes within the spirit and scope of the invention as defined by the claims. Further, in order to make the public have a better understanding of the present invention, some specific details are described in detail in the detailed description of the present invention below. The present invention can be fully understood by those skilled in the art without the description of these detailed parts.

[0027] First of all, what needs to be understood is that the standard answer generation method of an o...

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Abstract

The invention discloses a standard answer generation method of an on-line Verilog code automatic judgment system. According to the title, correct Verilog code is compiled, a. Vwf waveform file is edited and simulated to generate. Do and. Vt files; . Do file and. Vt file are analyzed and modified to generate new. Do file and. Vt file; a standard answer.cmp file is generated to load into the answerlibrary; each file in the invention constructs the operation of the whole Verilog answer decision system, and ensures that the decision system can give a correct result.

Description

technical field [0001] The invention relates to online code automatic judgment in the field of online education, in particular to a standard answer generation method for an online Verilog code automatic judgment system. Background technique [0002] In the online education process of EDA (Electronic Design Automatic) course, the brand-new online education method of Verilog code judgment has been widely used; the key to realize the function of Verilog code judgment is to design and implement a A set of algorithms for Verilog code analysis, simulation and judgment, especially the generation of standard answers to Verilog programming questions and the generation of files required for the judgment process; in traditional technologies, it is usually a system for judging questions about c or c++ codes, Applied to the ACM competition, there is no system for judging Verilog code. Contents of the invention [0003] The embodiment of the present invention provides a standard answer...

Claims

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Application Information

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IPC IPC(8): G06F8/41G06F8/30G06F8/75G06Q50/20
CPCG06F8/30G06F8/41G06F8/75G06Q50/205
Inventor 黄继业谢尚港陆燕怡马德曾毓
Owner HANGZHOU DIANZI UNIV
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