A standard answer generation method for an on-line Verilog code automatic decision system

Abstract

The invention discloses a standard answer generation method of an on-line Verilog code automatic judgment system. According to the title, correct Verilog code is compiled, a. Vwf waveform file is edited and simulated to generate. Do and. Vt files; . Do file and. Vt file are analyzed and modified to generate new. Do file and. Vt file; a standard answer.cmp file is generated to load into the answerlibrary; each file in the invention constructs the operation of the whole Verilog answer decision system, and ensures that the decision system can give a correct result.

Description

technical field [0001] The invention relates to online code automatic judgment in the field of online education, in particular to a standard answer generation method for an online Verilog code automatic judgment system. Background technique [0002] In the online education process of EDA (Electronic Design Automatic) course, the brand-new online education method of Verilog code judgment has been widely used; the key to realize the function of Verilog code judgment is to design and implement a A set of algorithms for Verilog code analysis, simulation and judgment, especially the generation of standard answers to Verilog programming questions and the generation of files required for the judgment process; in traditional technologies, it is usually a system for judging questions about c or c++ codes, Applied to the ACM competition, there is no system for judging Verilog code. Contents of the invention [0003] The embodiment of the present invention provides a standard answer...

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Problems solved by technology

[0002] In the online education process of EDA (Electronic Design Automatic) course, the brand-new online education method of Verilog code judgment has been widely used; the key to realize the function of Verilog code judgment is to design and implement a A set of algorithms for Verilog code analysis, simulation and judgment, especially the generation of standard answers to Verilog programming questions and the generation of files required for the judgment process; in traditional technologies, it is usually a system for judging questions about c or c++ codes, Applied to the ACM competition, there is no system for verilog code judgment

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