Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

A pipelined analog-to-digital converter comparator offset front calibration circuit and method

An analog-to-digital converter and calibration circuit technology, applied in analog/digital conversion calibration/testing, analog/digital conversion, code conversion, etc., can solve the problem of inability to solve the dynamic offset error of the comparator, and achieve strong technical portability , the effect of occupying a small chip area

Active Publication Date: 2022-05-13
BEIJING MXTRONICS CORP +1
View PDF13 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In recent years, many digital calibration methods for comparator offset calibration have appeared, but they mainly focus on solving the static offset error of the comparator, but cannot solve the dynamic offset error of the comparator.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A pipelined analog-to-digital converter comparator offset front calibration circuit and method
  • A pipelined analog-to-digital converter comparator offset front calibration circuit and method
  • A pipelined analog-to-digital converter comparator offset front calibration circuit and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0057] The circuits and methods provided by the present invention, calibrated for the key module comparator in the pipelined analog-to-digital converter, can greatly reduce the offset error of the comparator, while not introducing excessive power consumption. This technology has been successfully used in the first and second stages of a 16-bit pipelined analog-to-digital converter. The maximum absolute value of the offset voltage of the original comparator is about ±60mV, and after using this calibration technique to set the cycle comparison number to 65536, the maximum absolute value of the offset voltage drops to about ±1mV. The integral error of the converter is inl when the calibration method is not used, and the maximum value can reach about 20LSB, such as Figure 5 as shown. After using this calibration method, the maximum value is only about 2LSB, such as Figure 6 as shown. Compared with other inventions, the present invention does not introduce static power consumption when...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A pipelined analog-to-digital converter comparator offset calibration circuit and method, including a current source I1 and an adjustable resistor string unit array, the adjustable resistor string unit array includes N adjustable resistor string units RESL1-RESLN, and the power supply VDD and The current source I1 and the adjustable resistor string units RESL1 - RESLN are sequentially connected in series between the grounds. The adjustable resistor string units RESL1 - RESLN have the same structure and adjustable resistance. The adjustable resistor string unit includes 4 trimming resistors R1~R4, 5 switches SW1~SW5, 1 binary alternative switch DSW, comparator COMP, accumulator ACCU, threshold decision device THR and bidirectional shift register SHREG. The invention divides the traditional divider resistor into four for fine-tuning the offset voltage of the comparator without introducing additional static power consumption, and is especially suitable for low-power consumption design.

Description

Technical field [0001] The present invention relates to the field of integrated circuits, is a pipelined analog-to-digital converter comparator offset front-end calibration circuit and method, mainly used in low-power pipelined analog-to-digital converters. Background [0002] In the design of pipelined analog-to-digital converters, device mismatches due to process deviations and imbalances in the parasitic inductance capacitance of the switch can cause the comparator to be out of balance, which seriously affects the performance of the analog-to-digital converter. Generally, increasing the size of the device can reduce its offset but will lead to a serious increase in power consumption, so how to reduce the comparator offset without increasing the power consumption is one of the research focuses of the current pipelined analog-to-digital converter design. [0003] The traditional comparator offset calibration mainly uses an analog method to measure the offset voltage of the comp...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009
Inventor 纪亚飞王勇王宗民张铁良王瑛冯文晓李雪杨龙邴兆航郭瑞靳翔
Owner BEIJING MXTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products