A pipelined analog-to-digital converter comparator offset front calibration circuit and method
An analog-to-digital converter and calibration circuit technology, applied in analog/digital conversion calibration/testing, analog/digital conversion, code conversion, etc., can solve the problem of inability to solve the dynamic offset error of the comparator, and achieve strong technical portability , the effect of occupying a small chip area
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[0057] The circuits and methods provided by the present invention, calibrated for the key module comparator in the pipelined analog-to-digital converter, can greatly reduce the offset error of the comparator, while not introducing excessive power consumption. This technology has been successfully used in the first and second stages of a 16-bit pipelined analog-to-digital converter. The maximum absolute value of the offset voltage of the original comparator is about ±60mV, and after using this calibration technique to set the cycle comparison number to 65536, the maximum absolute value of the offset voltage drops to about ±1mV. The integral error of the converter is inl when the calibration method is not used, and the maximum value can reach about 20LSB, such as Figure 5 as shown. After using this calibration method, the maximum value is only about 2LSB, such as Figure 6 as shown. Compared with other inventions, the present invention does not introduce static power consumption when...
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